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340 SA-1110 Developer’s Manual
Peripheral Control Module
The receive FIFO contains three bits (8, 9, and 10) that are not directly readable. The 9th bit in the
FIFO is set at the top of the FIFO whenever a byte of data that incurs a framing error is moved from
the receive serial shifter to the top of the receive FIFO. This tag travels along with the errant data
value as it moves down the FIFO. Each time a data value is transferred to the bottom of the FIFO
(caused by a read of the previous value), the state of this bit is moved from the FIFO to the FRE bit in
the status register. After the error in FIFO (EIF) status bit is set, the user should always read UTSR1
first to check FRE before reading the data value from UDR because FRE corresponds to the current
data byte at the bottom of the receive FIFO and is updated each time data is removed from the FIFO.
11.11.8.6 Receiver Overrun Flag (ROR) (read-only, noninterruptible)
The receiver overrun status bit (ROR) is set when the receive logic attempts to place data into the
receive FIFO after it has been completely filled.
The receive FIFO contains three bits (8, 9, and 10) that are not directly readable. The 10th bit in the
FIFO is set within the top entry of the receive FIFO whenever an overrun occurs. This tag travels
along with the last “good” data value before the overflow occurred as it moves down the FIFO.
Each time a data value is transferred to the bottom of the FIFO (caused by a read of the previous
value), the state of this bit is moved from the FIFO to the ROR bit in the status register, indicating
that the next value in the FIFO is the last “good” piece of data before the overflow occurred. After
the error in FIFO (EIF) status bit is set, the user should always read UTSR1 first to check ROR
before reading the data value from UDR because ROR corresponds to the current data byte at the
bottom of the receive FIFO and is updated each time data is removed from the FIFO.