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164 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
Figure 10-10. Burst-of-Eight ROM or Flash Read Timing Diagram
A6639-02
Memory Clock
nCS0
RDN+1
A[25:5]
A[4:2]
nCS1
nOE
RD/nWR
01234567
RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1
RDF+1.5
RDF+2
max* (2*RRR,1)
Contents of static memory register fields:
MSC0:RDF0=8 MSC0:RDN0=4 MSC0:RRR0=2
Input Data