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80 SA-1110 Developer’s Manual
System Control Module
9.1.1.6 GPIO Alternate Function Register (GAFR)
The GPIO alternate function register (GAFR) contains 28 control bits that correspond to the 28
GPIO port pins. When the processor sets a bit in the GAFR, the corresponding GPIO pin is
switched over to that pin’s alternate function. See the following section for details on alternate
functions. This register is cleared to all zeros on all reset conditions.
0h 9004 001C GAFR Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
AF27
AF26
AF25
AF24
AF23
AF22
AF21
AF20
AF19
AF18
AF17
AF16
AF15
AF14
AF13
AF12
AF11
AF10
AF9
AF8
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
nAFn
GPIO alternate function bits (where n = 0 through 27).
A bit set in this register indicates that the corresponding GPIO pin is to be used for its
alternate function. A zero in this register indicates that the corresponding GPIO pin is to be
used for its normal GPIO function.
31..28 — Reserved