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422 SA-1110 Developer’s Manual
Boundary-Scan Test Interface
Table 16-2 shows the SA-1110 correspondence between boundary-scan cells and system pins,
system direction controls and system output enables.
KeytoTable:
IN Input pad
OUT Output pad
EN Enable
OEL Output enable latch
OEL
†
Output enable latch for nWE, nOE, nSDRAS, nSDCAS, nRAS 0,
nCAS[3:0], A[25:0]
ICL Input capture latch
OCL Output capture latch
VDCL Voltage differential capture latch
Table 16-2. Boundary-Scan Signals and Pins (Sheet 1 of 4)
No. Pin Type BS Cell
BS
Function
Guard
Value
EX
No. Pin Type BS Cell
BS
Function
Guard
Value
EX
from TDI
1 BATT_FAULT IN qjti ICL 35 D 10 IN qjti ICL
2 VDD_FAULT IN qjti ICL 36 D 18 OUT qjto OCL
3 PWR_EN OUT qjtogp OCL 37 D 18 IN qjti ICL
4 SFRM_C EN qjtena OEL 38 D 26 OUT qjto OCL
5 SFRM_C OUT qjto OCL 39 D 26 IN qjti ICL
6 SFRM_C IN qjti ICL 40 D 3 OUT qjto OCL
7 SCLK_C EN qjtena OEL 41 D 3 IN qjti ICL
8 SCLK_C OUT qjto OCL 42 D 11 OUT qjto OCL
9 SCLK_C IN qjti ICL 43 D 11 IN qjti ICL
10 RXD_C EN qjtena OEL 44 D 19 OUT qjto OCL
11 RXD_C OUT qjto OCL 45 D 19 IN qjti ICL
12 RXD_C IN qjti ICL 46 D 27 OUT qjto OCL
13 TXD_C EN qjtena OEL 46 D 27 IN qjti ICL
14 TXD_C OUT qjto OCL 48 D 4 OUT qjto OCL
15 TXD_C IN qjti ICL 49 D 4 IN qjti ICL
16 D 0 OUT qjto OCL 50 D 12 OUT qjto OCL
17 D 0 IN qjti ICL 51 D 12 IN qjti ICL
18 D 8 OUT qjto OCL 52 D 20 OUT qjto OCL
19 D 8 IN qjti ICL 53 D 20 IN qjti ICL
20 D 16 OUT qjto OCL 54 D 28 OUT qjto OCL
21 D 16 IN qjti ICL 55 D 28 IN qjti ICL
22 D 24 OUT qjto OCL 56 D 5 OUT qjto OCL
23 D 24 IN qjti ICL 57 D 5 IN qjti ICL
24 D 1 OUT qjto OCL 58 D 13 OUT qjto OCL
25 D 1 IN qjti ICL 59 D 13 IN qjti ICL
26 D 9 OUT qjto OCL 60 D 21 OUT qjto OCL
27 D 9 IN qjti ICL 61 D 21 IN qjti ICL
28 D 17 OUT qjto OCL 62 D 29 OUT qjto OCL
29 D 17 IN qjti ICL 63 D 29 IN qjti ICL
30 D 25 OUT qjto OCL 64 D 6 OUT qjto OCL
31 D 25 IN qjti ICL 65 D 6 IN qjti ICL
32 D 2 OUT qjto OCL 66 D 14 OUT qjto OCL
33 D 2 IN qjti ICL 67 D 14 IN qjti ICL
34 D 10 OUT qjto OCL 68 D 22 OUT qjto OCL