Filter
Top Products
168 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
Figure 10-13. SRAM Write Timing Diagram (4–Beat Burst)
In Figure 10-13 some of the parameters are defined as follows:
tAS = Address setup to nCS = 1 CPU cycle
tCES = nCS, nCAS/DQM setup to nWE = 2 memory clock cycles (4 CPU cycles)
tASW = Address setup to nWE low (asserted) = 1/2 memory cycle (1 CPU cycle)
[For A[25:5], tASW=5 CPU cycles. For A[4:2], tASW=1 CPU cycle for subsequent beats in a burst]
tDSWH = Write data setup to nWE high (deasserted) = 1/2 memory cycle + (RDN+1) memory cycles
tDH = Data hold after nWE high (deasserted) = 1/2 memory cycle (1 CPU cycle)
tCEH = nCS, nCAS/DQM held asserted after nWE deasserted = 1 memory clock cycle (2 CPU
cycles)
tAH = Address hold after nWE deasserted = 1/2 memory cycle (1 CPU cycle)
nWE high time between burst beats = 1 memory cycle (2 CPU cycles)
A6643-02
Memory Clock
t
AS
t
AH
t
DSWH
t
ASW
t
CEH
max(2*RRR,1)
A[25:0]
nCS0
D[31:0]
nCAS[3:0]
nWE
RD/nWR
A0
D0 D1 D2 D3
A0+4 A0+8 A0+12
t
DH
t
CES
RDN+1 RDN+1 RDN+1RDN+1
Contents of static memory register fields:
MSC0: RDN0=2 MSC0:RRR0=2