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SA-1110 Developer’s Manual 101
System Control Module
Note: When in idle mode, if the BATT_FAULT and/or VDD_FAULT pins are asserted, the SA-1110
enters sleep mode.
9.5.3 Sleep Mode
Sleep mode offers the greatest power savings and, consequently, the lowest level of available
functionality. In the transition from run or idle to sleep mode, the SA-1110 performs an orderly
shutdown of on-chip activity, applies an internal reset to the processor, and then negates the
PWR_EN pin indicating to the external system that the VDDI (1.5-V supply) can be driven to zero
volts. Internally, this switches off the power to the majority of the processor at this time. (The
VDDX I/O voltage supply must remain powered during sleep.) Running off the 32.768-kHz crystal
oscillator, the sleep state machine watches for a preprogrammed wake-up event to occur, after
which it asserts PWR_EN (to reestablish the VDDI power supply), and steps through an orderly
wake-up sequence. When the power supply and clocks are stable, the power manager brings the
SA-1110 out of reset. Status bits in the reset controller status register (RCSR) may be read to
indicate to software that the reset was due to sleep mode.
9.5.3.1 CPU Preparation for Sleep Mode
In preparation for sleep mode, software initializes the power manager GPIO sleep state register
(PGSR) and the power manager wake-up enable register (PWER). Also, the GPIO falling-edge
detect and GPIO rising-edge detect enable registers (GFER and GRER) should be written with the
appropriate values. The OPDE bit in the power manager configuration register (PCFR) should also
be programmed with the desired value.
9.5.3.2 Events Causing Entry into Sleep Mode
Sleep mode is entered in one of two ways: through software control or a power supply fault. Entry
into sleep mode through software is accomplished by setting the force sleep bit in the power
manager control register (PMCR). This bit is set by software and cleared by hardware during sleep.
When the SA-1110 wakes up from sleep, this bit is already cleared.
Entry into sleep via a power supply fault is caused by the assertion of either the VDD_FAULT or
BATT_FAULT pins. The VDD_FAULT pin should be used to indicate that the main power supply
is out of regulation. The BATT_FAULT pin should be used to indicate that the battery has been
removed or is low. These pins have identical operation for the purpose of entering sleep mode.
They have different implications during the wake-up sequence as described in the following
section.
9.5.3.3 The Sleep Shutdown Sequence
The sleep state machine begins the shutdown sequence. This sequence consists of three steps.
• In the first step, the following actions occur:
a. Power manager switches the GPIO output pins to their sleep state. This sleep state is
programmed in advance by loading the power manager GPIO sleep state register (PGSR)
into the GPIO output data register. (See the Section 9.1, “General-Purpose I/O” on
page 9-73.)
b. The DRAMs are placed into self-refresh mode. The memory controller finishes whatever
memory operation might be in progress, issues a self-refresh command to SDRAM, and
drives the nRAS/nSDCS[3:0] and nCAS/DQM[3:0] pins low.