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352 SA-1110 Developer’s Manual
Peripheral Control Module
11.12.3.5 A/D Sampling Mode (ADM)
The A/D sampling mode (ADM) bit selects whether the MCP takes audio and telecom data from
the incoming frame only when their respective data valid bits are set or whenever the MCP’s audio
and telecom sample rate counters time-out, indicating that the data in the next incoming frame is
valid. When ADM=0, data is taken from the incoming frame and is placed into the audio or
telecom FIFO whenever the incoming audio or telecom data valid bit is set. When ADM=1, after
the MCP is enabled, data is taken from the incoming frame when the data valid bit is set for the
first time. After this point, the data valid bit is ignored, and samples are stored each time the audio
or telecom sample rate counters decrement to zero, indicating that a new A-to-D sample was taken
and will be available in the next frame.
The UCB1x00 has two different modes of operation to control the setting of the audio and telecom
data valid bits. In one mode, the codec only sets the data valid bit when a new A-to-D sample is
contained within the incoming data frame. Once the data is transmitted to the MCP within a receive
data frame, the data valid bit is reset to zero for subsequent data frames until a new A-to-D sample
is triggered and transmitted to the MCP. In this mode, the user should program ADM=0. In the
other mode, the data valid bit is set once when the first A-to-D conversion is made and is placed in
the receive data frame. However, the data valid bit remains set and the MCP cannot determine
when new A-to-D conversions are available within the incoming frame. Programming ADM=1
prevents multiple copies of the same A-to-D conversion to be placed in the FIFO, storing samples
only when the sample rate counter times out.
11.12.3.6 Telecom Transmit FIFO Interrupt Enable (TTE)
The telecom transmit FIFO interrupt enable (TTE) bit is used to mask or enable the telecom
transmit FIFO service request interrupt. When TTE=0, the interrupt is masked and the state of the
telecom transmit FIFO service request (TTS) bit within the MCP status register is ignored by the
interrupt controller. When TTE=1, the interrupt is enabled, and whenever TTS is set (one), an
interrupt request is made to the interrupt controller. Note that programming TTE=0 does not affect
the current state of TTS or the telecom transmit FIFO logic’s ability to set and clear TTS; it only
blocks the generation of the interrupt request. Also note that TTE does not affect generation of the
telecom transmit FIFO DMA request, which is asserted any time TTS=1.
11.12.3.7 Telecom Receive FIFO Interrupt Enable (TRE)
The telecom receive FIFO interrupt enable (TRE) bit is used to mask or enable the telecom receive
FIFO service request interrupt. When TRE=0, the interrupt is masked, and the state of the telecom
receive FIFO service request (TRS) bit within the MCP status register is ignored by the interrupt
controller. When TRE=1, the interrupt is enabled, and whenever TRS is set (one), an interrupt
request is made to the interrupt controller. Note that programming TRE=0 does not affect the
current state of TRS or the telecom receive FIFO logic’s ability to set and clear TRS; it only blocks
the generation of the interrupt request. Also note that TRE does not affect generation of the telecom
receive FIFO DMA request, which is asserted any time TRS=1.
11.12.3.8 Audio Transmit FIFO Interrupt Enable (ATE)
The audio transmit FIFO interrupt enable (ATE) bit is used to mask or enable the audio transmit
FIFO service request interrupt. When ATE=0, the interrupt is masked and the state of the audio
transmit FIFO service request (ATS) bit within the MCP status register is ignored by the interrupt
controller. When ATE=1, the interrupt is enabled, and whenever ATS is set (one), an interrupt
request is made to the interrupt controller. Note that programming ATE=0 does not affect the