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402 SA-1110 Developer’s Manual
AC Parameters
NOTES:
1. These input pins may be sampled on either the rising or falling edge of the memory clock.
2. These signals are PCMCIA outputs and are driven by a state machine clocked by BCLK. The user defines
BCLK by programming the number of processor clocks per BCLK. Two processor clocks make one memory
clock cycle. To ensure proper operation, the user must adhere to the protocol description.
3. These signals are PCMCIA inputs and are sampled by a state machine clocked by BCLK. The user defines
BCLK by programming the number of processor clocks per BCLK. Two processor clocks make one memory
clock cycle. To ensure proper operation, the user must adhere to the protocol description.
4. These output pins may be driven on either the rising or falling edge of the memory clock
5. These AC timing guidelines are for asynchronous memory types. Each parameter references the SA-1110’s
internal memory clock. These parameters are not guaranteed for use under all operating conditions.
Table 13-4. SA-1110 AC Timing Guidelines for Asynchronous Memory Types
Pin Name Symbol Parameter Min Max Unit Note
Memory Bus
D[31:0]
Tdfov
Memory clock fall to D[31:0] driven valid
— 10 ns 5
Tds D[31:0] valid to memory clockrise/fall (input setup) 3 — ns 1, 5
Tdh Memory clock rise/fall to data invalid (input hold) 3 — ns 1, 5
nPOE, nPWE, nPIOR,
nPIOW, PSKTSEL,
nPREG, nPCE[1,2],
A[25:0]
Tmfov Memory clock fall to output driven valid — 10 ns
2, 5
5
5
5
nIOIS16
Tio16s nIOIS16 valid to memory clock rise (input setup) 3 — ns 3, 5
Tio16h
Memory clock rise to nIOIS16 invalid (input hold)
3 — ns 3, 5
nPWAIT
Twaits nPWAIT valid to memory clock fall (input setup) 3 — ns 5
Twaith
Memory clock fall to nPWAIT invalid (input hold)
3 — ns 5
nWE, nOE Tmrov Memory clock rise to output driven valid — 10 ns
5
5
nRAS/nSDCS[3:0] Tmrdv
Memory clock rise to output driven valid
— 12 ns 5
nCAS/DQM[3:0] Tcasd
Memory clock rise/fall to nCAS/DQM[3:0] driven
valid
— 12 ns 4, 5
nCS[5:0] Tcsd
Memory clock rise to nCS[5:0] driven valid
— 10 ns 5
RDY
Trdys RDY valid to memory clock rise/fall (input setup) 3 — ns 5
Trdyh
Memory clock rise/fall to RDY invalid (input hold)
3 — ns 5
RD/nWR Trdnwr
Memory clock rise/fall to RD/nWR driven valid
— 10 ns 5
SDCLK[2:0] Tsdclk
Memory clock rise to SDCLK[2:0] driven valid
2.8 10.8 ns 5
Table 13-5. SA-1110 AC Timing Table: MCP Interface and LCD Controller (Sheet 1 of 2)
Pin Name Symbol Parameter Min Max Unit Note
MCP (CODEC) Interface
SFRM_C Tsfrmv SCLK_C rise to SFRM_C driven valid — 21 ns —
RXD_C
Trxds RXD_C valid to SCLK_C fall (input setup) 11 — ns —
Trxdh SCLK_C fall to RXD_C invalid (input hold) 0 — ns —
TXD_C Ttxdv SCLK_C rise to TXD_C valid — 22 ns —
LCD Controller
L_LDD[7:0] Tpclkdv L_PCLK rise/fall to L_LDD[7:0] driven valid — 14 ns 1