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84 SA-1110 Developer’s Manual
System Control Module
9.2.1 Interrupt Controller Register Definitions
The interrupt controller contains four registers: the interrupt controller IRQ pending register
(ICIP), the interrupt controller FIQ pending register (ICFP), the interrupt controller mask register
(ICMR), and the interrupt controller level register (ICLR). Following reset, the FIQ and IRQ
interrupts are disabled within the CPU, and the states of all of the interrupt controller’s registers are
unknown and must be initialized by software before interrupts are enabled within the CPU.
9.2.1.1 Interrupt Controller Pending Register (ICPR)
The ICPR is a 32-bit read-only register that shows all active interrupts in the system. These bits are
not affected by the state of the mask register (ICMR). The following table shows the pending
interrupt source assigned to each bit position in the ICPR. Also included in the table are the source
units for the interrupts and the number of second-level interrupts associated with each. For more
detail on the second-level interrupts, see the section describing that unit.
Bit Position Unit Source Module # of Level 2 Sources Bit Field Description
IP 31
System
Real-time clock
1 RTC equals alarm register.
IP 30 1 One Hz clock TIC occurred.
IP 29
Operating system timer
1 OS timer equals match register 3.
IP 28 1 OS timer equals match register 2.
IP 27 1 OS timer equals match register 1.
IP 26 1 OS timer equals match register 0.
IP 25
Peripheral
DMA controller
3 Channel 5 service request.
IP 24 3 Channel 4 service request.
IP 23 3 Channel 3 service request.
IP 22 3 Channel 2 service request.
IP 21 3 Channel 1 service request.
IP 20 3 Channel 0 service request.
IP 19 Serial port 4b 3 SSP service request.
IP 18 Serial port 4a 8 MCP service request.
IP 17 Serial port 3 6 UART service request.
IP 16 Serial port 2 6+6 UART/HSSP service request.
IP 15 Serial port 1b 6 UART service request.
IP 14 Reserved
—
Reserved.
IP 13 Serial port 0 6 UDC service request.
IP 12 LCD controller 12 LCD controller service request.