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SA-1110 Developer’s Manual 311
Peripheral Control Module
11.10.6.4 Transmit Enable (TXE)
The transmit enable (TXE) bit is used to enable and disable HSSP transmit operation. When
TXE=0, the transmit logic is disabled and its clocks are turned off to conserve power. When
TXE=1, the HSSP transmitter logic is enabled for IrDA transmission. It is required that the user
first program all other control bits before setting TXE. If the TXE bit is cleared to zero while the
HSSP is actively transmitting data, transmission is stopped immediately, all data within the
transmit FIFO and serial output shifter is cleared, and control of the TXD2 pin is given to the
peripheral pin control (PPC) unit. When the transmitter is turned on (TXE=0→1), a SIP pulse is
transmitted before transmission of data. A SIP pulse is used to prevent slower devices (115.2 Kbps)
from attempting to take control of infrared transmission. See the previous sections for further
timing details of the SIP pulse.
TXE and RXE are the only HSCR0 control bits within the HSSP that are initialized when a
hardware reset occurs. Clearing TXE to zero ensures the HSSP transmitter is disabled, giving
control of the transmit pin to the PPC unit that configures TXD1 as an input following a reset of the
SA-1110. Note that TXE is ignored when ITR=0 (enables UART operation). Also note that even
though the IrDA standard permits only half-duplex operation, the HSSP does not restrict the user
from transmitting and receiving data at the same time; both are fully independent units. This
function is particularly useful when using the HSSP in loopback mode. See the Section 11.10.6.2,
“Loopback Mode (LBM)” on page 11-310.
11.10.6.5 Receive Enable (RXE)
The receive enable (RXE) bit is used to enable or disable HSSP receive operation. When RXE=0, the
receive logic is disabled and its clocks are turned off to conserve power. When RXE=1, the HSSP
receiver logic is enabled for IrDA reception. It is required that the user first program all other control
bits before setting RXE. If the RXE bit is cleared to zero while the HSSP is actively receiving data,
reception is stopped immediately, all data within the receive FIFO and serial input shifter is cleared,
and control of the RXD2 pin is given to the peripheral pin control (PPC) unit. Note that TXE and
RXE are the only control bits within the HSSP that are initialized when a hardware reset occurs.
Clearing RXE to zero ensures the HSSP receiver is disabled, giving control of the receive pin to the
PPC unit, which configures RXD2 as an input following a reset of the SA-1110. Note that RXE is
ignored when ITR=0, which enables UART operation. Also note that even though the IrDA standard
permits only half-duplex operation, the HSSP does not restrict the user from transmitting and
receiving data at the same time; both are fully independent units. This function is particularly useful
when using the HSSP in loopback mode. See the Section 11.10.6.2, “Loopback Mode (LBM)” on
page 11-310.
11.10.6.6 Receive FIFO Interrupt Enable (RIE)
The receive FIFO interrupt mask (RIE) bit is used to mask or enable the receive FIFO service
request interrupt. When RIE=0, the interrupt is masked, and the state of the receive FIFO service
request (RFS) bit within HSSP status register 0 is ignored by the interrupt controller. When RIE=1,
the interrupt is enabled, and whenever RFS is set (one), an interrupt request is made to the interrupt
controller. Note that programming RIE=0 does not affect the current state of RFS or the receive
FIFO logic’s ability to set and clear RFS; it only blocks the generation of the interrupt request.
Also note that RIE does not affect generation of the receive FIFO DMA request , which is asserted
whenever RFS=1.