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12 SA-1110 Developer’s Manual
11.11.1.1Frame Format................................................................................................326
11.11.1.2Baud Rate Generation...................................................................................326
11.11.1.3Receive Operation.........................................................................................326
11.11.1.4Transmit Operation........................................................................................327
11.11.1.5Transmit and Receive FIFOs ........................................................................327
11.11.1.6CPU and DMA Register Access Sizes..........................................................327
11.11.2 UART Register Definitions ...........................................................................................327
11.11.3 UART Control Register 0..............................................................................................328
11.11.3.1Parity Enable (PE).........................................................................................328
11.11.3.2Odd/Even Parity Select (OES) ......................................................................328
11.11.3.3Stop Bit Select (SBS) ....................................................................................328
11.11.3.4Data Size Select (DSS).................................................................................329
11.11.3.5Sample Clock Enable (SCE) .........................................................................329
11.11.3.6Receive Clock Edge Select (RCE)................................................................329
11.11.3.7Transmit Clock Edge Select (TCE) ...............................................................329
11.11.4 UART Control Registers 1 and 2..................................................................................330
11.11.4.1Baud Rate Divisor (BRD) ..............................................................................330
11.11.5 UART Control Register 3..............................................................................................331
11.11.5.1Receiver Enable (RXE) .................................................................................332
11.11.5.2Transmitter Enable (TXE)..............................................................................332
11.11.5.3Break (BRK) ..................................................................................................332
11.11.5.4Receive FIFO Interrupt Enable (RIE) ............................................................332
11.11.5.5Transmit FIFO Interrupt Enable (TIE)............................................................333
11.11.5.6Loopback Mode (LBM) ..................................................................................333
11.11.6 UART Data Register.....................................................................................................334
11.11.7 UART Status Register 0 ...............................................................................................335
11.11.7.1Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)336
11.11.7.2Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt) 336
11.11.7.3Receiver Idle Status (RID) (read/write, maskable interrupt)..........................336
11.11.7.4Receiver Begin of Break Status (RBB) (read/write, nonmaskable interrupt).337
11.11.7.5Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)....337
11.11.7.6Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt) ........................337
11.11.8 UART Status Register 1 ...............................................................................................339
11.11.8.1Transmitter Busy Flag (TBY) (read-only, noninterruptible)............................339
11.11.8.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible) ..............339
11.11.8.3Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible) ..................339
11.11.8.4Parity Error Flag (PRE) (read-only, noninterruptible) ....................................339
11.11.8.5Framing Error Flag (FRE) (read-only, noninterruptible) ................................339
11.11.8.6Receiver Overrun Flag (ROR) (read-only, noninterruptible)..........................340
11.11.9 UART Register Locations.............................................................................................341
11.12Serial Port 4 – MCP / SSP ......................................................................................................342
11.12.1 MCP Operation.............................................................................................................343
11.12.1.1Frame Format................................................................................................343
11.12.1.2Audio and Telecom Sample Rates and Data Transfer..................................345
11.12.1.3MCP Transmit and Receive FIFO Operation ................................................346
11.12.1.4Codec Control Register Data Transfer ..........................................................347
11.12.1.5External Clock Operation ..............................................................................348