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SA-1110 Developer’s Manual 3
Contents
1 Introduction
1.1 Intel® StrongARM SA-1110 Microprocessor ..............................................................................21
1.2 Overview .....................................................................................................................................24
1.3 Example System .........................................................................................................................25
1.4 ARM Architecture........................................................................................................................26
1.4.1 26-Bit Mode ....................................................................................................................26
1.4.2 Coprocessors .................................................................................................................26
1.4.3 Memory Management.....................................................................................................26
1.4.4 Instruction Cache............................................................................................................26
1.4.5 Data Cache.....................................................................................................................26
1.4.6 Write Buffer.....................................................................................................................27
1.4.7 Read Buffer ....................................................................................................................27
2 Functional Description
2.1 Block Diagram.............................................................................................................................29
2.2 Inputs/Outputs.............................................................................................................................31
2.3 Signal Description .......................................................................................................................32
2.4 Memory Map ...............................................................................................................................36
3 ARM Implementation Options
3.1 Big and Little Endian ...................................................................................................................39
3.2 Exceptions...................................................................................................................................39
3.2.1 Power-Up Reset .............................................................................................................40
3.2.2 ROM Size Select ............................................................................................................40
3.2.3 Abort...............................................................................................................................41
3.2.4 Vector Summary.............................................................................................................42
3.2.5 Exception Priorities.........................................................................................................42
3.2.6 Interrupt Latencies and Enable Timing...........................................................................43
3.3 Coprocessors..............................................................................................................................43
4 Instruction Set
4.1 Instruction Set .............................................................................................................................45
4.2 Instruction Timing........................................................................................................................45
5 Caches, Write Buffer, and Read Buffer
5.1 Instruction Cache (Icache) ..........................................................................................................47
5.1.1 Icache Operation ............................................................................................................47
5.1.2 Icache Validity ................................................................................................................47
5.1.2.1 Software Icache Flush..................................................................................... 47
5.1.3 Icache Enable/Disable and Reset ..................................................................................48
5.1.3.1 Enabling the Icache......................................................................................... 48
5.1.3.2 Disabling the Icache........................................................................................ 48
5.2 Data Caches (Dcaches)..............................................................................................................48
5.2.1 Cacheable Bit – C...........................................................................................................49
5.2.1.1 Cacheable Reads – C = 1............................................................................... 49