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18 SA-1110 Developer’s Manual
13-1 Memory Bus AC Timing Definitions..........................................................................................398
13-2 LCD AC Timing Definitions.......................................................................................................399
13-3 MCP AC Timing Definitions ......................................................................................................400
14-1 SA-1110 256-Pin mBGA Mechanical Drawing ......................................................................... 406
16-1 Test Access Port (TAP) Controller State Transitions ...............................................................413
16-2 Boundary-Scan Block Diagram ................................................................................................417
16-3 Boundary-Scan General Timing ...............................................................................................419
16-4 Boundary-Scan Tristate Timing ................................................................................................420
16-5 Boundary-Scan Reset Timing...................................................................................................420
Tables
1-2 Changes to the SA-1110 Core from the SA-110 ........................................................................22
1-1 Features of the SA-1110 CPU....................................................................................................22
1-3 Feature Additions to the SA-1110 from the SA-110 ...................................................................23
1-4 Feature Additions to the SA-1110 from the SA-1100 .................................................................23
2-1 Signal Descriptions.....................................................................................................................32
3-1 Vector Summary.........................................................................................................................42
4-1 Instruction Timing .......................................................................................................................45
5-1 Effects of the Cacheable and Bufferable Bits on the Data Caches ............................................49
6-1 Cache and MMU Control Registers (Coprocessor 15) ...............................................................56
7-1 Valid MMU, Dcache, and Write Buffer Combinations.................................................................66
8-1 Core Clock Configurations..........................................................................................................70
9-1 OS Timer Register Locations .....................................................................................................99
9-2 SA-1110 Power and Clock Supply Sources and States During Power-Down Modes ..............106
9-3 Pin State During Sleep .............................................................................................................107
9-4 Power Manager Register Locations .........................................................................................114
9-5 Reset Controller Register Locations.........................................................................................117
10-1 Supported Memory Types ........................................................................................................119
10-2 SA-1110 Transactions On 32-Bit Data Buses .......................................................................... 123
10-3 Memory Interface Control Registers.........................................................................................127
10-4 Timing Interpretations of Possible SDRAM/SMROM MDCAS Settings ................................... 139
10-5 BS_xx Bit Encoding ..................................................................................................................143
10-6 BCLK Speeds for 160-MHz Processor Core Frequency ..........................................................143
10-7 Some DRAM Memory Size Options ......................................................................................... 148
10-8 DRAM or SMROM Row/Column Address Multiplexing ............................................................149
10-9 SDRAM Command Encoding ...................................................................................................154
10-10 Summary of Static Memory and Variable Latency I/O Capabilities ..........................................162
10-11 SMROM Command Encoding ..................................................................................................174
11-1 Peripheral Control Modules’ Register Width and DMA Port Size .............................................206
11-2 Peripheral Unit Base Addresses...............................................................................................207
11-3 Peripheral Unit Interrupt Numbers............................................................................................207
11-4 Dedicated Peripheral Pins ........................................................................................................208
11-5 Peripheral Unit GPIO Pin Assignment...................................................................................... 209
11-6 Valid Settings for the DDARn Register.....................................................................................213
11-7 8-Bits Per Pixel Data Memory Organization (Little Endian)......................................................224
11-8 Color/Gray-Scale Intensities and Modulation Rates.................................................................227
11-9 LCD Controller Data Pin Utilization ..........................................................................................230