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298 SA-1110 Developer’s Manual
Peripheral Control Module
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11.9.4 GPCLK Control Registers 2 and 3
GPCLK Control Register 2 (GPCLKR2) contains the upper 4 bits and GPCLK Control Register 3
(GPCLKR3) the lower 8 bits of the baud rate divisor field.
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11.9.4.1 Baud Rate Divisor (BRD)
The 12-bit baud rate divisor (BRD) field is used to select the baud or bit rate of the GPCLK output
clock. A total of 4096 different baud rates can be selected, ranging from a minimum of
900 Hz to 3.6864 MHz. The baud rate generator uses the 3.6864-MHz clock generated by the
on-chip PLL and first divides it by the programmable baud rate using BRD. The resultant clock is
sent out GPIO pin 16. The resultant baud rate given a specific BRD value, or required BRD value
given a desired baud rate, can be calculated using the following two respective equations, where
BRD is the decimal equivalent of the unsigned binary value programmed within the bit field:
The following tables show the bit locations corresponding to the baud rate divisor field that is split
between two registers. The upper 4 bits of BRD reside within GPCLKR1and the lower 8 bits reside
within GPCLKR2. The GPCLK must be disabled (SUS=0) whenever these registers are written.
Note that writes to reserved bits are ignored and reads return zeros; question marks indicate that the
values are unknown at reset.
0h 8002 0064 GPCLKR1 Read/Write
7 6 5 4 3 2 1 0
Reserved
TXE Reserved
Reset
? ? ? ? ? ? 0 ?
Bits Name Description
1TXE
Transmit Enable
0 – GPCLK Transmit Logic disabled. Control of he TXD1 pin is given to the PPC unit if
SUS=0
1– GPCLK Transmit Logic enabled if SUS=0.
7.. 2 and 0 — Reserved.
BaudRate
3.6864
6
×10
BRD 1+()
-------------------------------=
BRD
3.6864
6
×10
BaudRate
-------------------------------1–=