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SA-1110 Developer’s Manual 357
Peripheral Control Module
11.12.5.2 MCP Data Register 1
When MCP data register 1 (MCDR1) is read, the bottom entry of the telecom receive FIFO is
accessed. As data is removed by the MCP’s receive logic from the incoming data frame, it is placed
into the top entry of the telecom receive FIFO and is transferred down an entry at a time until it
reaches the last empty location within the FIFO. Data is removed by reading MCDR1, which
accesses the bottom entry of the telecom FIFO. After MCDR1 is read, the bottom entry is
invalidated, and all remaining values within the FIFO automatically transfer down one location.
When MCDR1 is written, the topmost entry of the telecom transmit FIFO is accessed. After a
write, data is automatically transferred down to the lowest location within the transmit FIFO,
which does not already contain valid data. Data is removed from the bottom of the FIFO one value
at a time by the transmit logic, is loaded into the correct position within the 64-bit transmit serial
shifter, and then is serially shifted out onto the TXD4 pin during subframe 0.
The following table shows MCDR1. Note that the transmit and receive telecom FIFOs are cleared
when the SA-1110 is reset, or by writing a zero to MCE (MCP disabled). Also note that writes to
reserved bits are ignored and reads return zeros.
0h 8006 0008 MCP Data Register 0: MCDR0 Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Bottom of Audio Receive FIFO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read Access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Top of Audio Transmit FIFO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Write Access
Bits Name Description
15..0 Audio Data
Transmit/receive audio FIFO data.
Read – Bottom of audio receive FIFO data.
Write – Top of audio transmit FIFO data.
31..16 — Reserved.