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SA-1110 Developer’s Manual 361
Peripheral Control Module
ARE has no effect on the generation of the DMA service request. After the DMA or CPU fills the
FIFO such that four or more locations are filled within the receive FIFO, the ARS flag (and the
service request and/or interrupt) is automatically cleared.
11.12.6.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only,
maskable interrupt)
The telecom transmit FIFO service request flag (TTS) is a read-only bit that is set when the
telecom transmit FIFO is nearly empty and requires service to prevent an underrun. TTS is set
whenever the telecom transmit FIFO has four or fewer entries of valid data (half-full or less), and is
cleared when it has five or more entries of valid data. When the TTS bit is set, an interrupt request
is made unless the telecom transmit FIFO interrupt request mask (TTE) bit is cleared. The state of
TTS is also sent to the DMA controller, and can be used to signal a DMA service request. Note that
TTE has no effect on the generation of the DMA service request. After the DMA or CPU fills the
FIFO such that four or more locations are filled within the telecom transmit FIFO, the TTS flag
(and the service request and/or interrupt) is automatically cleared.
11.12.6.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only,
maskable interrupt)
The telecom receive FIFO service request flag (TRS) is a read-only bit that is set when the telecom
receive FIFO is nearly filled and requires service to prevent an overrun. TRS is set whenever the
telecom receive FIFO has four or more entries of valid data (half-full or more), and is cleared when
it has three or fewer (less than half-full) entries of data. When the TRS bit is set, an interrupt
request is made unless the telecom receive FIFO interrupt request mask (TRE) bit is cleared. The
state of TRS is also sent to the DMA controller, and can be used to signal a DMA service request.
Note that TRE has no effect on the generation of the DMA service request. After the DMA or CPU
fills the FIFO such that four or more locations are filled within the receive FIFO, the TRS flag (and
the service request and/or interrupt) is automatically cleared.
11.12.6.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, nonmaskable
interrupt)
The audio transmit FIFO underrun status bit (ATU) is set when the audio transmit logic attempts to
fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the audio
transmit logic continuously transmits the last valid audio value, which was transmitted before the
underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the
audio transmit logic uses the new value within the FIFO for transmission. When the ATU bit is set,
an interrupt request is made.
11.12.6.6 Audio Receive FIFO Overrun Status (ARO) (read/write, nonmaskable
interrupt)
The audio receive FIFO overrun status bit (ARO) is set when the audio receive logic attempts to
place data into the audio receive FIFO after it has been completely filled. Each time a new piece of
data is received, the set signal to the ARO status bit is asserted, and the newly received data is
discarded. This process is repeated for each new piece of data received until at least one empty
FIFO entry exists. When the ARO bit is set, an interrupt request is made.