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SA-1110 Developer’s Manual 57
Coprocessors
6.2.2 Register 1 – Control
Register 1 is a read/write register containing control bits. All writable bits in this register are forced
low by reset. The shaded bits (also labeled r) are reserved and are not readable or writable..
Register 1 – Control Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined
XI
Undefined
RS
B
111WCAM
(Sheet 1 of 2)
Bits Name Description
0M
Enable/disable
0 – On-chip memory-management unit disabled
1 – On-chip memory-management unit enabled
1A
Address fault enable/disable
0 – Alignment fault disabled
1 – Alignment fault enabled
2C
Data cache enable/disable
0 – Data cache disabled
1 – Data cache enabled
3W
Write buffer enable/disable
0 – Write buffer disabled
1 – Write buffer enabled
4P
32-bit/26-bit exception handlers.
Should always be 1.
5D
32-bit/26-bit Data address range.
Should always be 1.
6L
Implementation defined.
Should always be 1.
7B
Big/little endian
0 – Little endian operation
1 – Big endian operation
8S
System
This bit selects the access checks performed by the memory-management unit.
See the ARM Architecture Reference for more information.
9R
ROM
This bit selects the access checks performed by the memory-management unit.
See the ARM Architecture Reference for more information.
11..10 —
Unused.
Undefined on Read. Writes ignored.
12 I
Instruction cache enable/disable
0 – Instruction cache disabled
1 – Instruction cache enabled