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106 SA-1110 Developer’s Manual
System Control Module
9.5.6 Pin Operation in Sleep Mode
The SA-1110 pins are categorized by the following types based on their behavior during sleep mode:
• Type 1 – These pins are outputs and are driven low during sleep. These pins hold their state
after sleep mode is exited until the DRAM_control_hold bit in the PSSR is cleared.
• Type 1b – These pins are outputs and are driven low during sleep. These pins are actively
driven immediately after sleep mode is exited.
• Type 2 – These pins are outputs and are normally driven to a one in sleep. To support systems
that power down external devices, these pins can also be tristated in sleep through the use of
the FLOAT_STATIC and FLOAT_PCMCIA bits in the PCFR. See the Section 9.5, “Power
Manager” on page 9-99.
• Type 2b – These pins are outputs and are normally driven to a one in sleep. These pins are
actively driven immediately after sleep mode is exited.
• Type 3 – These pins are I/O pins. When programmed as outputs, they can be actively held high
or low during sleep. When programmed as inputs, they are actively sampled by the SA-1110.
• Type 4 – These pins are I/O pins but become inputs during sleep. They can be programmed to
hold the pin state at a zero or can be tristated. The receivers on these pins are disabled during
sleep. These pins hold their state after sleep mode is exited until the peripheral_control_hold
bit in the PSSR is cleared.
• Type 5 – These pins are outputs and are actively driven during sleep.
• Type 6 – These pins are outputs and are tristated during sleep.
Table 9-2. SA-1110 Power and Clock Supply Sources and States During Power-Down Modes
Power Management Mode
Module
Supply Source Run Idle Sleep
Pwr Clk Pwr Clk Pwr Clk Pwr Clk
CPU
VDD
3.6864
MHz
On Running On
Stopped
Disabled
Stopped
MMUs (I&D)
Write buffer
Read buffer
JTAG
Running
OS timer
LCD controller
Serial channel 0-4
Memory and
PCMCIA
control
Real-time clock
VDDX 32.768
kHz
On Running
Interrupt
controller
Power manager
General-purpose I/O
Pin pads