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282 SA-1110 Developer’s Manual
Peripheral Control Module
The TIM bit must be initialized before enabling the SA-1110 UDC.
11.8.3.7 Suspend Interrupt Mask (SUSIM)
The SUSIM bit masks or enables the suspend interrupt.
• When the SUSIM bit is written to 1, the suspend interrupt is masked and the SUSIR bit in the
UDC Status/Interrupt Register is not allowed to be set.
• When the SUSIM bit is written to 0, the suspend interrupt is enabled. Whenever a suspend
condition occurs, the SUSIR bit in the UDC Status/Interrupt Register is automatically set to 1.
Note: The CPU writing a 1 to the SUSIM bit does not affect the current state of SUSIR. Rather, it blocks
future zero–to–one transitions of the SUSIR bit.
11.8.3.8 Reserved/B5
The Reserved/B5 bit is “reserved” in A0, B0, B1, B2, and B4 steppings of the SA-1110 and must
be cleared to zero.
For the B5 stepping of the SA-1110:
• The Reserved/B5 bit must be set to 1 (by writing a 1 to it) to activate the internal fix for Errata
29.
• The SA-1110 UDC must first be connected to a USB Host before the Reserved/B5 bit can be
set to 1. The Reserved/B5 bit must be set to 1 each time that the USD is connected or
re-connected to a USB Host.
Note: The stepping of the SA-1110 can be determined by reading Coprocessor 15 Register 0 (see section
5.2.1). For B5 stepping, CP15, R0[3:0] should read 0x1001
11.8.4 UDC Address Register (UDCAR)
UDCAR contains seven bits that hold the UDC’s address. After a reset of the SA-1110 UDC, the
address value is zero. Software parses the SET_ADDRESS command received by the SA-1110
UDC from the Host to extract the address that the Host has assigned to the SA-1110 UDC.
Software then writes the address to the UDCAR, but the address does not enter the UDCAR until
after USB interface software completes an Acknowledgement Handshake back to the Host.