Filter
Top Products
SA-1110 Developer’s Manual 281
Peripheral Control Module
• When the RESIM bit is written to 1, the resume interrupt is masked and the RESIR bit in the
UDC Status/Interrupt Register cannot be set.
• When the RESIM bit is written to 0, the resume interrupt is enabled. Whenever a resume
condition occurs, the RESIR bit in the UDC Status/Interrupt Register is automatically set to 1.
A resume condition occurs after a suspend condition has occurred. A write of a 1 followed by a
write of a 0 to the RESIM bit resets the internal suspend state machine so future resume conditions
are recognized.
Note: The CPU writing a 1 to the RESIM bit does not affect the current state of the RESIR bit. Rather, it
blocks future zero–to–one transitions of the RESIR bit.
11.8.3.4 Endpoint 0 Interrupt Mask (EIM)
The EIM bit is used to mask or enable the Endpoint 0 interrupt.
• When the EIM bit is written to 1, the Endpoint 0 interrupt is masked and the EIR bit in the
UDC Status/Interrupt Register cannot be set.
• When EIM is written to 0, the Endpoint 0 interrupt is enabled. Whenever an interruptible
condition occurs in the receiver of Endpoint 0, the EIR bit in the UDC Status/Interrupt
Register is automatically set to 1.
Note: The CPU writing a 1 to the EIM bit does not affect the current state of the EIR bit. Rather, it blocks
future zero–to–one transitions of the EIR bit.
11.8.3.5 Receive Interrupt Mask (RIM)
The RIM bit is used to mask or enable the Endpoint 1 receive interrupt.
• When the RIM bit is written to 1, the receive interrupt is masked and the RIR bit in the UDC
Status/Interrupt Register cannot be set.
• When the RIM bit is written to 0, the receive interrupt is enabled. Whenever an interruptible
condition occurs in the receiver of Endpoint 1, the RIR bit in the UDC Status/Interrupt
Register is automatically set to 1.
Note: The CPU writing a 1 to the RIM bit does not affect the current state of the RIR bit. Rather, it blocks
future zero-to-one transitions of the RIR bit.
The RIM bit must be initialized before enabling the SA-1110 UDC.
11.8.3.6 Transmit Interrupt Mask (TIM)
The TIM bit is used to mask or enable the Endpoint 2 transmit interrupt.
• When the TIM bit is written to 1, the transmit interrupt is masked and the TIR bit in the UDC
Status/Interrupt Register cannot be set.
• When the TIM bit is written to 0, the transmit interrupt is enabled. Whenever an interruptible
condition occurs in the transmitter of Endpoint 2, the TIR bit is automatically set to 1.
Note: The CPU writing a 1 to the TIM bit does not affect the current state of the TIR bit. Rather, it blocks
future zero-to-one transitions of the TIR bit.