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SA-1110 Developer’s Manual 427
Register Summary A
This appendix describes all of the Intel
®
StrongARM
*
SA-1110 Microprocessor (SA-1110)
internal registers.
Physical Address Symbol Register Name
UDC Registers (Serial Port 0)
0h 8000 0000 UDCCR UDC control register.
0h 8000 0004 UDCAR UDC address register.
0h 8000 0008 UDCOMP UDC OUT max packet register.
0h 8000 000C UDCIMP UDC IN max packet register.
0h 8000 0010 UDCCS0 UDC endpoint 0 control/status register.
0h 8000 0014 UDCCS1 UDC endpoint 1 (out) control/status register.
0h 8000 0018 UDCCS2 UDC endpoint 2 (in) control/status register.
0h 8000 001C UDCD0 UDC endpoint 0 data register.
0h 8000 0020 UDCWC UDC endpoint 0 write count register.
0h 8000 0024 — Reserved.
0h 8000 0028 UDCDR UDC transmit/receive data register (FIFOs).
0h 8000 002C — Reserved.
0h 8000 0030 UDCSR UDC status/interrupt register.
UART Registers (Serial Port 1)
0h 8001 0000 UTCR0 UART control register 0.
0h 8001 0004 UTCR1 UART control register 1.
0h 8003 0008 UTCR2 UART control register 2.
0h 8001 000C UTCR3 UART control register 3.
0h 8001 0010 — Reserved.
0h 8001 0014 UTDR UART data register.
0h 8001 0018 — Reserved.
0h 8001 001C UTSR0 UART status register 0.
0h 8001 0020 UTSR1 UART status register 1.
0h 8001 0024 – 0h 8001 FFFF — Reserved.
GPCLK Registers (Serial Port 1)
0h 8002 0060 GPCLKR0 GPCLK Control Register 0.
0h 8002 0064 — GPCLK Control Register 1.
0h 8002 0068 — Reserved.
0h 8002 006C GPCLKR1 GPCLK Control Register 2.
0h 8002 0070 GPCLKR2 GPCLK Control Register 3.
0h 8002 0074 — Reserved.