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148 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
10.5 Dynamic Interface Operation
This section describes the dynamic memory interface.
Note: There is an online memory configuration tool at http://appzone.intel.com/hcd/sa1110/memory
which can be used to help configure the SA-1110 for operation with the user’s choice of memory.
10.5.1 DRAM Overview
The dynamic memory interface supports up to four banks, organized as two bank pairs. Both banks
within a pair must have the same DRAM size, configuration, timing type, and data bus width.
Initialization software must set up the memory interface configuration registers with the DRAM
timing type, data bus width, number of row address bits, nCAS/DQM waveforms, and timing
parameters. The SA-1110 generates accesses of 1-8 words.
Table 10-7 shows some of the supported DRAM configurations.
Table 10-7. Some DRAM Memory Size Options
Bank Size
(Mbyte/Bank)
DRAM
Configuration
(Words x Bits)
Chip Size
Number Chips /
Bank
Row bits x
Column Bits
Maximum
Memory
(4 Banks,
32-bit Bus)
Total Number
of Chips
16-bit
Bus
32-bit
Bus
16-bit
Bus
32-bit
Bus
16-bit
Bus
32-bit
Bus
16-bit
Bus
32-bit
Bus
512
Kbyte
1
Mbyte
256Kx16 4Mbit 1 2 9x9
10 x 8
2
Mbyte
4
Mbyte
48
1
Mbyte
2
Mbyte
512Kx8 4Mbit 2 4 10x9 4
Mbyte
8
Mbyte
816
2
Mbyte
4
Mbyte
1 M x 4 4Mbit 4 8 10 x 10 8
Mbyte
16
Mbyte
16 32
2
Mbyte
4
Mbyte
1Mx16 16Mbit 1 2 10x10
12 x 8
8
Mbyte
16
Mbyte
48
4
Mbyte
8
Mbyte
2Mx8 16Mbit 2 4 11x10
12 x 9
16
Mbyte
32
Mbyte
816
8
Mbyte
16
Mbyte
4Mx4 16Mbit 4 8 11x11
12 x 10
32
Mbyte
64
Mbyte
16 32
8
Mbyte
16
Mbyte
4Mx16 64Mbit 1 2 11x11
12 x 10
13 x 9
14 x 8
32
Mbyte
64
Mbyte
48
16
Mbyte
32
Mbyte
8Mx8 64Mbit 2 4 12x11
13 x 10
14 x 9
64
Mbyte
128
Mbyte
816
32
Mbyte
64
Mbyte
16 M x 4 64 Mbit 4 8 12 x 11
13 x 11
14 x 10
128
Mbyte
256
Mbyte
16 32
32
Mbyte
64
Mbyte
16 M x 16 256 Mbit 1 2 15 x 9 128
Mbyte
256
Mbyte
48
64
Mbyte
128
Mbyte
32 M x 8 256 Mbit 2 4 15 x 10 256
Mbyte
512
Mbyte
816
128
Mbyte
N/A 64 M x 4 256 Mbit 4 N/A 15 x 11 512
Mbyte
N/A 16 N/A