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SA-1110 Developer’s Manual 247
Peripheral Control Module
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11.7.10 DMA Channel 2 Base and Current Address Registers
DMA channel 2’s base and current address registers (DBAR2 and DCAR2) function exactly like
DMA channel 1’s except that they are used exclusively for dual-panel operation. (See the preceding
sections.) When SDS=1, DMA channel 2 is used to supply frame buffer data to the lower half of the
display. Note that the palette buffer, which resides within the first 16 or 256 entries of the frame buffer,
is utilized only by DMA channel 1. The user should not place palette entries into the frame buffer for
DMA channel 2. The base address for channel 2 points to the first encoded pixel values for the lower
half of the display. For dual-panel operation, the user must perform the following sequence in order:
disable the LCD (LEN=0), program dual-panel mode (SDS= 0
→ 1), write the upper panel DMA base
address, write the lower DMA base address and enable the LCD (LEN= 0
→ 1). The following figures
show the format of these registers; question marks indicate that the values are unknown at reset.
0h B010 0014
DCAR1: DMA Channel 1 Current
Address Register
Read Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA Channel 1 Current Address Pointer
Reset
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Bits Name Description
31..0 DCAR1
DMA channel 1 current address pointer.
Read-only register. Continuously reflects the current physical address that DMA channel 1
is transferring from or will use in the next transfer. Base address register is transferred to
this register whenever the LCD is enabled (LEN= 0 → 1) and when the current address is
equal to the calculated end address of the buffer.