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8 SA-1110 Developer’s Manual
11.7.1.6 Output FIFO...................................................................................................227
11.7.1.7 LCD Controller Pins .......................................................................................227
11.7.2 LCD Controller Register Definitions .............................................................................228
11.7.3 LCD Controller Control Register 0................................................................................229
11.7.3.1 LCD Enable (LEN) .........................................................................................229
11.7.3.2 Color/Monochrome Select (CMS)..................................................................229
11.7.3.3 Single-/Dual-Panel Select (SDS) ...................................................................229
11.7.3.4 LCD Disable Done Interrupt Mask (LDM) ......................................................231
11.7.3.5 Base Address Update Interrupt Mask (BAM).................................................232
11.7.3.6 Error Interrupt Mask (ERM)............................................................................232
11.7.3.7 Passive/Active Display Select (PAS) .............................................................232
11.7.3.8 Big/Little Endian Select (BLE)........................................................................233
11.7.3.9 Double-Pixel Data (DPD) Pin Mode...............................................................234
11.7.3.10Vertical Slant Line Correction (VSC).............................................................234
11.7.3.11Palette DMA Request Delay (PDD)...............................................................234
11.7.4 LCD Controller Control Register 1................................................................................236
11.7.4.1 Pixels Per Line (PPL).....................................................................................237
11.7.4.2 Horizontal Sync Pulse Width (HSW)..............................................................237
11.7.4.3 End-of-Line Pixel Clock Wait Count (ELW)....................................................237
11.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW)..........................................237
11.7.5 LCD Controller Control Register 2................................................................................238
11.7.5.1 Lines Per Panel (LPP) ...................................................................................238
11.7.5.2 Vertical Sync Pulse Width (VSW) ..................................................................239
11.7.5.3 End-of-Frame Line Clock Wait Count (EFW).................................................239
11.7.5.4 Beginning-of-Frame Line Clock Wait Count (BFW) .......................................240
11.7.6 LCD Controller Control Register 3................................................................................241
11.7.6.1 Pixel Clock Divider (PCD)..............................................................................242
11.7.6.2 AC Bias Pin Frequency (ACB).......................................................................242
11.7.6.3 AC Bias Pin Transitions Per Interrupt (API)...................................................242
11.7.6.4 Vertical Sync Polarity (VSP) ..........................................................................243
11.7.6.5 Horizontal Sync Polarity (HSP)......................................................................243
11.7.6.6 Pixel Clock Polarity (PCP) .............................................................................243
11.7.6.7 Output Enable Polarity (OEP)........................................................................243
11.7.7 LCD Controller DMA Registers ....................................................................................245
11.7.8 DMA Channel 1 Base Address Register ......................................................................245
11.7.9 DMA Channel 1 Current Address Register ..................................................................246
11.7.10 DMA Channel 2 Base and Current Address Registers ................................................247
11.7.11 LCD Controller Status Register ....................................................................................248
11.7.11.1 LCD Disable Done Flag (LDD) (read/write, maskable interrupt) ..................249
11.7.11.2Base Address Update Flag (BAU) (read-only, maskable interrupt)...............249
11.7.11.3 Bus Error Status (BER) (read/write, maskable interrupt) .............................249
11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt) ...............249
11.7.11.5 Input FIFO Overrun Lower Panel Status (IOL)
(read/write, maskable interrupt) .....................................................................249
11.7.11.6 Input FIFO Underrun Lower Panel Status (IUL)
(read/write, maskable interrupt) .....................................................................250
11.7.11.7 Input FIFO Overrun Upper Panel Status (IOU)