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286 SA-1110 Developer’s Manual
Peripheral Control Module
Note: The CPU cannot clear the IPR bit.
11.8.7.3 Sent Stall (SST)
When, due to a protocol violation, the SA-1110 UDC aborts the current Control transfer by issuing
a STALL Handshake Packet, the SST bit is automatically set to 1 after the Stall response is sent on
the USB bus. When the SST bit is set, the EIR bit in the UDC Status/Interrupt Register will be
automatically set to 1 if Endpoint 0 interrupts are enabled. The CPU can clear the SST bit by
writing a 1 to it.
11.8.7.4 Force Stall (FST)
The FST bit is automatically set to 1 when the SA-1110 UDC needs Host intervention. After the
FST bit is set, the SA-1110 UDC issues a STALL Handshake Packet to the Host. This STALL
Handshake Packet is issued for the current SETUP Control transfer only; the FST bit is then
automatically cleared to 0 (after Stall is sent on the USB bus) so that Endpoint 0 does not remain in
the stalled condition.
11.8.7.5 Data End (DE)
The DE bit is automatically set to 1 after the SA-1110 UDC writes the last Data Packet for the
current descriptor. The DE bit needs to be set to 1 by the CPU when the last bytes of the packet do
not fill the 8 byte FIFO, for example, the last 2 bytes of an 18 byte packet. In this case, software
needs to set DE and clear OPR by writing a 0x50 to the UDCCS0 register. Once the current SETUP
Control transfer has ended, the DE bit is automatically cleared to 0. When the DE bit is cleared, the
EIR bit in the UDC Status/Interrupt Register will be automatically set to 1 if Endpoint 0 interrupts
are enabled. If there is no data phase, the CPU should write a 1 to the EIR bit at the same time that
it clears the OPR bit.
11.8.7.6 Setup End (SE)
The SE bit is automatically set to 1 when a Control transfer ends before the DE bit is set. When the
SE bit is set, the EIR bit in the UDC Status/Interrupt Register will be automatically set to 1 if
Endpoint 0 interrupts are enabled. The SE bit is cleared by the CPU writing a 1 to the SSE bit.
When the CPU detects that both the SE bit and OPR bit are set, the CPU should first clear the SE
bit by writing a 1 to the SSE bit, then unload the new Setup Packet.
11.8.7.7 Serviced OPR (SO)
Writing a 1 to the SO bit will clear the OPR bit to 0.
11.8.7.8 Serviced Setup End (SSE)
Writing a 1 to the SSE bit will clear the SE bit to 0.
11.8.8 UDC Endpoint 1 Control/Status Register (UDCCS1)
UDCCS1 contains six bits that are used to operate Endpoint 1 (OUT endpoint).