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170 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
Figure 10-14. Variable Latency I/O Read Timing (Burst-of-Four)
A6654-02
CPU
Clock
Memory
Clock
A(25:0)
nCS4
nWE
RD/nWR
D(31:0)
RDY
nOE
D1D0 D2 D3
t
AS
t
CES
t
ASRW0
RDF+1+WAITS
RDN+1
t
CEH
max(2*RRR,1)
t
AH
t
ASRWN
A0 A0+4 A0+8 A0+12
nCAS[3:0]
t
SS
Note: RDF = 2, RDN = 1, WAITS = 0 for this figure