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4 SA-1110 Developer’s Manual
5.2.1.2 Noncacheable Reads – C = 0..........................................................................49
5.2.2 Bufferable Bit – B ........................................................................................................... 49
5.2.3 Software Dcache Flush ..................................................................................................50
5.2.3.1 Doubly Mapped Space.....................................................................................50
5.2.4 Dcaches Enable/Disable and Reset...............................................................................50
5.2.4.1 Enabling the Dcaches ......................................................................................51
5.2.4.2 Disabling the Dcaches .....................................................................................51
5.3 Write Buffer (WB)........................................................................................................................51
5.3.1 Bufferable Bit..................................................................................................................51
5.3.2 Write Buffer Operation....................................................................................................51
5.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1) .............................51
5.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0) .......................52
5.3.2.3 Unbufferable and Noncacheable Writes (B=0, C=0)........................................52
5.3.2.4 Writes to a Non-Bufferable and Cacheable Location (B=0, C=1) ....................52
5.3.3 Enabling the Write Buffer ...............................................................................................52
5.3.3.1 Disabling the Write Buffer ................................................................................52
5.4 Read Buffer (RB) ........................................................................................................................ 52
6 Coprocessors
6.1 Internal Coprocessor Instructions ...............................................................................................55
6.2 Coprocessor 15 Definition...........................................................................................................56
6.2.1 Register 0 – ID ...............................................................................................................56
6.2.2 Register 1 – Control .......................................................................................................57
6.2.3 Register 2 – Translation Table Base ..............................................................................58
6.2.4 Register 3 – Domain Access Control .............................................................................58
6.2.5 Register 4 – RESERVED ...............................................................................................59
6.2.6 Register 5 – Fault Status................................................................................................59
6.2.7 Register 6 – Fault Address.............................................................................................59
6.2.8 Register 7 – Cache Control Operations .........................................................................59
6.2.9 Register 8 – TLB Operations..........................................................................................60
6.2.10 Register 9 – Read-Buffer Operations .............................................................................60
6.2.11 Registers 10 – 12 RESERVED ......................................................................................61
6.2.12 Register 13 – Process ID Virtual Address Mapping .......................................................61
6.2.13 Register 14 – Debug Support (Breakpoints) ..................................................................62
6.2.14 Register 15 – Test, Clock, and Idle Control....................................................................63
7 Memory Management Unit (MMU)
7.1 Overview.....................................................................................................................................65
7.1.1 MMU Registers...............................................................................................................65
7.2 MMU Faults and CPU Aborts......................................................................................................65
7.3 Data Aborts.................................................................................................................................65
7.3.1 Cacheable Reads (Linefetches) .....................................................................................66
7.3.2 Buffered Writes...............................................................................................................66
7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer.........................................................66
7.5 Mini Data Cache .........................................................................................................................67
8Clocks
8.1 Intel® StrongARM SA-1110 Crystal Oscillators..........................................................................69
8.2 Core Clock Configuration Register .............................................................................................70
8.2.1 Restrictions on Changing the Core Clock Configuration ................................................71