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92 SA-1110 Developer’s Manual
System Control Module
Note: When the AL bit goes high indicating that the alarm has occurred, the alarm interrupt bit (ALE)
must first be disabled (by writing a 0 to it) before the AL bit can be cleared (by writing a 0 to it).
3HZE
1-Hz interrupt enable.
0 – The 1-Hz interrupt is not enabled.
1 – The 1-Hz interrupt is enabled.
31..4 — Reserved
0h 9001 0010 RTSR Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
HZE
ALE
HZ
AL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ?
Bits Name Description