Filter
Top Products
SA-1110 Developer’s Manual 379
Peripheral Control Module
11.12.12 SSP Status Register
The SSP status register (SSSR) contains bits that signal overrun errors as well as the transmit and
receive FIFO service requests. Each of these hardware-detected events signals an interrupt request
to the interrupt controller. The status register also contains flags that indicate when the SSP is
actively transmitting characters, when the transmit FIFO is not full, and when the receive FIFO is
not empty (no interrupt generated).
A bit that can cause an interrupt signals the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read/write bits are called status bits; read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, must be cleared by software). Writing
a one to a sticky status bit clears it; writing a zero has no effect. Read-only flags are set and cleared
by hardware; writes have no effect. Additionally, some bits that cause interrupts have
corresponding mask/enable bits in the control registers and are indicated in the following section
headings. Note that the user has the ability to mask all SSP interrupts by clearing bit 19 within the
interrupt controller mask register (ICMR). See the Section 9.2, “Interrupt Controller” on
page 9-83.
11.12.12.1 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
The transmit FIFO not full flag (TNF) is a read-only bit that is set whenever the transmit FIFO
contains one or more entries that do not contain valid data and is cleared when the FIFO is
completely full. This bit can be polled when using programmed I/O to fill the transmit FIFO over
its halfway mark. This bit does not request an interrupt.
11.12.12.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
The receive FIFO not empty flag (RNE) is a read-only bit that is set whenever the receive FIFO
contains one or more entries of valid data and is cleared when it no longer contains any valid data.
This bit can be polled when using programmed I/O to remove remaining bytes of data from the
receive FIFO because DMA service and CPU interrupt requests are only made when four or more
bytes reside within the FIFO (3, 2, or 1 bytes may remain at the end of a frame). This bit does not
request an interrupt.
11.12.12.3 SSP Busy Flag (BSY) (read-only, noninterruptible)
The SSP busy (BSY) flag is a read-only bit that is set when the SSP is actively transmitting and/or
receiving data, and is cleared when the SSP is idle or disabled (SSE=0). This bit does not request
an interrupt.
11.12.12.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable
interrupt)
The transmit FIFO service request flag (TFS) is a read-only bit that is set when the transmit FIFO is
nearly empty and requires service to prevent an underrun. TFS is set whenever the transmit FIFO
has four or fewer entries of valid data (half-full or less), and is cleared when it has five or more
entries of valid data. When the TFS bit is set, an interrupt request is made unless the transmit FIFO
interrupt request enable (TIE) bit is cleared. The state of TFS is also sent to the DMA controller,
and can be used to signal a DMA service request. Note that TIE has no effect on the generation of
the DMA service request. After the DMA or CPU fills the FIFO such that four or more locations
are filled within the transmit FIFO, the TFS flag (and the service request and/or interrupt) is
automatically cleared.