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SA-1110 Developer’s Manual 129
Memory and PC-Card Control Module
11..8 TRP03..0
RAS precharge for bank pair 0/1.
TRP is encoded with the minimum number of memory clocks (minus 1) of nRAS/nSDCS
deassertion between transfers.
For SDRAM running at the full memory clock frequency, TRP determines the minimum
delay (TRP+1 memory cycles) from the first memory clock rising edge following data latch
for autoprecharge read command (READAP) to the memory clock edge upon which
subsequent row commands (bank activate, mode register set, self-refresh, or CBR) are
latched. The minimum delay from latching of READAP command to latching of subsequent
row commands is TDL+TRP+2 memory cycles. The minimum delay from command and
data latching for autoprecharge write (WRITEAP) to latching of subsequent row commands
is TRP+TWR+1 memory cycles. TRP must be written to a value of at least 1 for SDRAM.
The unit size for TRP is always the internal memory cycle, even if SDRAM is run at half the
memory clock frequency (MDREFR:K1DB2 = 1). However, for SDRAM running at half
frequency, the unit size for TDL is two memory cycles and TRP is effectively increased by
one because setup time for commands and write data is increased by one memory cycle.
13..12 TDL01..0
Data input latch after CAS deassertion for bank 0/1.
For asynchronous DRAM, TDL is encoded with he number of CPU clocks between the
deassertion of nCAS/DQM and latching of read data.
For SDRAM, TDL is encoded with the CAS latency (external SDCLK delay between
reception of the READ command and latching of the data). The unit size for TDL is the
external SDCLK cycle: when SDRAM is run at half the memory clock frequency
(MDREFR:K1DB2 = 1), the delay is 2*TDL internal memory cycles.
00 – 0 clocks for asynchronous DRAM. Reserved (DO NOT USE) for SDRAM.
01 – 1clocklater
10 – 2 clocks later.
11 – 3 clocks later.
For SDRAM, the MDCASxx registers provide an option to add one-half memory clock of
CAS latency to TDL. See Section 10.3.3.2 for a detailed description. Chapter 13, “AC
Parameters” provides frequency-dependent guidelines for using the delayed latching
option.
15..14 TWR01..0
SDRAM write recovery (write data to precharge delay) for bank pair 0/1
For SDRAM only. TWR is encoded with the number of memory clocks to be added to the
minimum precharge delay that follows write transfers. The unit size for TWR is always the
internal memory cycle, even if SDRAM is run at half the memory clock frequency
(MDREFR:K1DB2 = 1).
17..16 DE3..2
DRAM enables for bank 3 (bit 17) and bank 2 (bit 16)
For each DRAM bank, there is an enable bit. A single (nonburst) access (read or write) to a
disabled DRAM bank triggers a CBR refresh cycle to all banks. When all banks are
disabled, the refresh counter is disabled.
0 – DRAM bank disabled.
1 – DRAM bank enabled.
These bits are cleared by hardware or sleep reset.
18 DTIM2
DRAM timing type for bank pair 2/3.
0 – Asynchronous (FPM or EDO).
1 – Synchronous (SDRAM).
0h A000 0000 MDCNFG Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TWR21
TWR20
TDL21
TDL20
TRP23
TRP22
TRP21
TRP20
CDB22
DRAC22
DRAC21
DRAC20
DWID2
DTIM2
DE3
DE2
TWR01
TWR00
TDL01
TDL00
TRP03
TRP02
TRP01
TRP00
CDB20
DRAC02
DRAC01
DRAC00
DWID0
DTIM0
DE1
DE0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0
(Sheet 2 of 4)
Bits Name Description