Filter
Top Products
SA-1110 Developer’s Manual 215
Peripheral Control Module
The IE bit is the interrupt enable for the channel and is written by the user. An interrupt is generated
if the DONEA, DONEB, or ERROR bits are set, and the IE bit is set. The interrupt is negated when
all of these status bits are cleared.
The ERROR bit is set if the DMA controller is incorrectly programmed to point to reserved
memory space. No error is generated for references to nonexistent external memory. If interrupts
are enabled and the ERROR bit is set by the DMA controller, a channel interrupt will be generated.
The DONEA bit is a status bit set by the DMA controller to indicate the transfer to or from buffer
A has completed. If interrupts are enabled, DONEA being set results in a channel interrupt at the
end of the transfer.
The STRTA bit is set by the user to start the channel transfer to or from buffer A. When DONEA is
set, STRTA is cleared. The immediate action resulting from setting STRTA is dependent on the
state of the BIU bit.
The DONEB bit is a status bit set by the DMA controller to indicate the transfer to or from buffer B
has completed. If interrupts are enabled, DONEB being set results in a channel interrupt at the end
of the transfer.
The STRTB bit is set by the user to start the channel transfer to or from buffer B. When DONEB is
set, STRTB is cleared. The immediate action resulting from setting STRTB is dependent on the
state of the BIU bit.
The BIU status bit indicates the current buffer-in-use (A or B) if a DMA transfer is in process on
the channel. If BIU is a zero, buffer A is in use. If BIU is a one, buffer B is in use. When no DMA
transfers are in process on the channel, the BIU bit indicates the buffer to be used for the next DMA
transfer initiated on the channel. If BIU is a zero, buffer A is utilized next; if BIU is a one, buffer B
is used next. The setting of DONEA or DONEB by the DMA controller toggles the BIU bit. For
example, if a DMA transfer utilizing buffer A is in process, the DONEA bit would be a zero and
the BIU bit would also be zero. After the transfer completed, the DONEA bit would be a one
indicating the buffer A activity was complete, and the BIU bit would toggle to a one indicating
buffer B is the next buffer to be utilized. Note that it is not sufficient for system software to only
interrogate the BIU bit to determine if a DMA transfer is in process on a channel. The STARTn,
DONEn, and BIU bits must be examined to determine if a DMA transfer is in process on the
channel. The BIU bit must not be cleared by system software (see note below) and is only cleared
by the DMA controller at reset (either hardware, software, watchdog, or sleep). For this reason, the
processor must interrogate the BIU bit before programming the channel for a new transfer to
determine which buffer (A or B) to use. If both STRTA and STRTB are set at the same time, the
first buffer serviced depends on the state of BIU. Buffer A will be serviced first if BIU is a zero;
otherwise, buffer B will be serviced first if BIU is a one.
Note: Never clear the BIU bit by writing to DCSR_Clear because this leaves the DMA status register bit
BIU (viewed via DCSR_Read) in an undefined state and can only be recovered by reset. Always
write 0x7F to DCSR_Clear to clear DCSRn bits 6 - 0 before programming the DMA channel.
11.6.1.3 DMA Buffer A Start Address Register (DBSAn)
The DBSAn is a 32-bit read/write register which contains the starting physical memory address for
buffer A memory region. For DMA write transfers to a serial controller device utilizing buffer A,
this is the starting physical memory address of the outbound data to be written to the device. For
DMA read transfers from a serial controller device utilizing buffer A, this is the starting physical
memory address of where the inbound data from the device being read are stored. This register may
be written only while the STRTA bit in the DCSRn is zero.