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SA-1110 Developer’s Manual 285
Peripheral Control Module
take place. This can be accomplished by writing to a SA-1110 UDC register and then reading back
the same register two times. The second read-back should produce correct data.
11.8.7.1 OUT Packet Ready (OPR)
The OPR bit is automatically set to 1 when a valid Token Packet is received from the Host into
Endpoint 0. When the OPR bit is set, the EIR bit in the UDC Status/Interrupt Register will be
automatically set to 1 if Endpoint 0 interrupts are enabled. The OPR bit is cleared to 0 by the CPU
writing a 1 to the SO bit of UDCCS0. The SA-1110 UDC is not allowed to enter the Data Packet
phase of a Control transaction until the OPR bit is cleared. If there is no Data Packet phase, then the
CPU should write a 1 to the DE bit of UDCCS0 (to set it) at the same time it clears the OPR bit.
11.8.7.2 IN Packet Ready (IPR)
After the CPU writes a DATA0 Data Packet to the Control FIFO for transmission to the Host, the
CPU writes a 1 to the IPR bit to set it. The SA-1110 UDC will automatically clear the IPR bit to 0
when the DATA0 Data Packet has been successfully transmitted to the Host. When the IPR bit is
cleared, the EIR bit in the UDC Status/Interrupt Register will be automatically set to 1 if Endpoint
0 interrupts are enabled.
0h 8000 0010 UDCCS0 Read/Write
7 6 5 4 3 2 1 0
SSE SO SE DE FST SST IPR
OPR
Reset
0 0 0 0 0 0 0 0
Bits Name Description
0OPR
OUT packet ready (read-only).
1 – OUT packet ready.
1IPR
IN packet ready (read/write 1 to set).
1 – IN packet ready.
2SST
Sent stall (read/write 1 to clear).
1 – SA-1110 UDC sent stall handshake.
3FST
Force stall (read/write 1 to set).
1 – Force stall handshake.
4DE
Data end (read/write 1 to set).
1 – The last byte of the data phase has been written.
5SE
Setup end (read-only).
1 – Control transfer ended before DE bit was set.
6SO
Serviced OPR (write-only).
1 – Clear OPR, bit 0.
7SSE
Serviced setup end (write-only).
1 – Clear SE, bit 5.