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278 SA-1110 Developer’s Manual
Peripheral Control Module
9. Return from interrupt.
10. Repeat step 3 until all of the data has been read from the Host.
Case 7: EP2 Data Transmit (Bulk-IN)
1. At this point in the program, software, has received a SETUP VENDOR command setting up
an EP2-BULK-IN transaction. Software has configured the DMA engine and enabled the EP2
interrupt to feed the DMA engine to handle the data.
2. During the SETUP VENDOR command, software sets up the DMA to write data from
memory to the UDCDR FIFO. Software determines the amount of data to be transferred and if
it is less than the maximum packet value indicated in the UDCIMP register it reprograms the
UDCIMP register with the byte amount to be transferred (bytes –1). For the DMA engine
channel used, software determines the current active buffer and provides the DMA the current
data buffer pointer. It then increments its data buffer index accordingly.
3. The Host sends a BULK-IN request.
4. The SA-1110 UDC sends a PACKET back to the Host and generates an EP2 interrupt.
5. The software checks the UDCCS2-TPC and UDCCS2-TFS bits are set to 1 to ensure validity
of the other register bits and the Transmit FIFO needs service, i.e. it has 8 bytes or less in it.
6. The Transmit DMA channel is paused.
7. If the UDCCS2-TUR and UDCCS2-TPE bits are set, software decrements its data pointer to
resend the data.
8. The DMA engine is restarted, i.e. repeat step 2, software clears the UDCCS2-TPC bit.
9. Return from interrupt.
10. Repeat step 3 until all the bulk data has been sent to the Host.
11.8.1.10 SA-1110 USB Example Code
Example code can be found at http://developer.intel.com/design/strong/swsup/
11.8.2 SA-1110 UDC Register Definitions
All configuration, request/service, and status reporting is controlled by the Host and is
communicated to the SA-1110 UDC via the USB bus. Several registers are available to the
programmer to facilitate responding to and controlling the SA-1110 UDC via software. The
SA-1110UDCControlRegister(UDCCR)isusedtoenabletheSA-1110UDCandtomaskthe
various interrupt sources that exist within the SA-1110 UDC. The UDC Status/Interrupt Register
(UDCSR) is used to indicate the state of the various interrupt sources.
Software parses the SET_ADDRESS command received by the SA-1110 UDC from the Host to
extract the address that the Host has assigned to the SA-1110 UDC. Software then writes the
address to the UDC Address Register (UDCAR), but the address does not enter the UDCAR until
after software completes an acknowledgement handshake back to the Host.
The UDC OUT Maximum Packet Register (UDCOMP) is used to specify the maximum packet
size of Endpoint 1 (Bulk OUT); the UDC IN Maximum Packet Register (UDCIMP) is used to
specify the maximum packet size of Endpoint 2 (Bulk IN).