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294 SA-1110 Developer’s Manual
Peripheral Control Module
• the FST bit is set to 1
11.8.13.2 Receive Interrupt Request (RIR)
The RIR bit gets automatically set to 1 if the RIM bit in UDCCR is cleared to 0 and the RPC bit in
UDCCS1 is set to 1. The RIR bit is cleared to 0 by the CPU writing a 1 to it.
11.8.13.3 Transmit Interrupt Request (TIR)
The TIR bit gets automatically set to 1 if the TIM bit in UDCCR is cleared to 0 and the TPC bit in
the UDCCS2 is set to 1. The TIR bit is cleared to 0 by the CPU writing a 1 to it.
11.8.13.4 Suspend Interrupt Request (SUSIR)
The SUSIR bit is automatically set to 1 if the SUSIM bit in UDCCR is cleared to 0 and the USB bus
remains idle for more than 3 milliseconds. The SUSIR bit is cleared to 0 by the CPU writing a 1 to it.
11.8.13.5 Resume Interrupt Request (RESIR)
The RESIR bit is cleared to 0 by the CPU writing a 1 to it. The RESIR gets automatically set to 1 if
all of the following occur:
• the RESIM bit in UDCCR is cleared to 0
• the UDC is currently in the suspended state
• the USB bus is driven with Resume signalling
11.8.13.6 Reset Interrupt Request (RSTIR)
The RSTIR bit gets automatically set to 1 if the REM bit in UDCCR is cleared to 0 and the Host
issues a reset. When the Host issues a reset, the entire SA-1110 UDC is reset, but the RSTIR bit
retains its state so software can determine that the SA-1110 UDC was reset. The RSTIR bit can be
cleared to 0 by the CPU writing a 1 to it.
11.8.14 SA-1110 UDC Register Locations
Table 11-14 shows the SA-1110 UDC registers and the physical addresses used to access them.
Table 11-14. SA-1110 UDC Control, Data, and Status Register Locations
Address Name Description
0h8000 0000 UDCCR UDC control register
0h8000 0004 UDCAR UDC address register
0h8000 0008 UDCOMP UDC OUT maximum packet register
0h8000 000C UDCIMP UDC IN maximum packet register
0h8000 0010 UDCCS0 UDC Endpoint 0 control/status register
0h8000 0014 UDCCS1 UDC Endpoint 1 (OUT) control/status register
0h8000 0018 UDCCS2 UDC Endpoint 2 (IN) control/status register