Filter
Top Products
SA-1110 Developer’s Manual 179
Memory and PC-Card Control Module
10.7.1 8-, 16-, and 32-Bit Data Bus Operation
The SA-1110 PC-Card interface supports only the 8- and 16-bit data bus operation outlined in the
PC-Card specification; the 32-bit operation supported by the SA-1110 is outside the scope of the
32-bit operation described in the PC-Card specification. The SA-1110 PC-Card interface’s 32-bit
operating mode is intended for use as a nonstandard expansion bus for communication with
customer-designed logic. The operation is fairly simple; if a word read or write is performed to
PC-Card memory space, then the entire 32-bit bus is read or written.
Normal PC-Card operations should be performed using byte or half-word accesses only. 32-bit
accesses should be word aligned and only to "16-bit" space, as opposed to 8-bit space. Memory and
attribute space is 16 bits by definition. However, I/O space may be 8- or 16-bit depending upon the
state of the nIOIS16 input pin. 32-bit accesses to I/O space require the target to assert nIOIS16.
For 32-bit accesses, the only size information present on the bus is the assertion of the nPCE1 and
nPCE2 pins. This is the same information that is present during half-word accesses. As such, there
is no way to determine by monitoring the SA-1110 pins whether the access is a half-word or word.
This information can be derived only though a user-defined address decode external to the
SA-1110. The following table shows the operation of the PC-Card interface and its relation to data
width.
Access Type
Data Bus
Width
1=16Bit
0=8Bit
Address [1:0] Resulting Operation
Word 1 00 Word read or write, nPCE1 and nPCE2 asserted (low).
nIOIS16 must be asserted for I/O space.
1x Undefined operation.
x1 Undefined operation.
0 xx Undefined operation.
Half-word 1 x0 (even) Single half-word access, nPCE1 and nPCE2 asserted
(low). nIOIS16 must be asserted for I/O space.
x1 (odd) Undefined operation.
0 x0 (even) Two-byte accesses, both on the lower byte lane. Even
access first (nPCE1 asserted and nPCE2 deasserted
for both).
x1 (odd) Undefined operation.
Byte 1 x0 (even) Load or store byte on the lower byte lane (nPCE1
asserted, nPCE2 deasserted).
x1 (odd) Load or store byte on the upper byte lane (nPCE1
deasserted, nPCE2 asserted).
0 xx (even or odd) Load or store byte on the low byte lane (nPCE2
deasserted and nPCE1 asserted).