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290 SA-1110 Developer’s Manual
Peripheral Control Module
11.8.9.4 Transmit Underrun (TUR)
The TUR bit is automatically set to 1 if the Transmit Data FIFO underruns. The TUR bit is valid
only when the TPC bit is set. When the FIFO underruns, the packet is shortened and the CRC is
corrupted, ensuring the Host discards the packet. The TUR bit is automatically cleared to 0 when
the TPC bit is cleared.
11.8.9.5 Sent STALL (SST)
The SST bit indicates a STALL Handshake was issued to the Host. The SST bit is cleared to 0 by
the CPU writing a 1 to it. When the SST bit is cleared, the Transmit Data FIFO is flushed.
11.8.9.6 Force STALL (FST)
The CPU can set the FST bit by writing a 1 to it to force the SA-1110 UDC to issue STALL
Handshakes to all IN Tokens. STALL Handshakes will continue to be sent by the SA-1110 UDC
until the CPU clears the FST bit to 0 by writing a 1 to it. The SST bit will be automatically set to 1
when the STALL state is actually entered (this may be delayed if the SA-1110 UDC is active when
theFSTbitisset).TheSTALLstatewillnotbeexiteduntilboththeFSTbitandtheSSTbitare
cleared to 0.
When the Host sends a command, such as ClearFeature(HALT), the SA-1110 UDC is required to
reinitialize its internal data toggle flag back to DATA0. To reinitialize this flag, the CPU must:
1. Set the FST bit to 1 by writing a 1 to it and read it back to ensure it is set.
2. Clear the FST bit by writing a 0 to it and read it back to ensure it is cleared.
3. Clear the SST bit by writing a 1 to it and read it back to ensure it is cleared.
11.8.10 UDC Endpoint 0 Data Register (UDCD0)
UDCD0 is actually an 8-bit x 8-entry bidirectional FIFO. When the Host transmits data to Endpoint
0, the CPU reads UDCD0 to access the data.
When the SA-1110 UDC is sending data to the Host, the CPU writes the data to be sent into the
UDCD0. Although the same Control FIFO can be read and written by the CPU during various
points in a control sequence, the CPU may not read from and write to the Control FIFO at the same
time. The direction that the Control FIFO is flowing is controlled by the SA-1110 UDC.
Normally, the SA-1110 UDC will be in an idle state, waiting for the Host to send commands. When
this happens, the SA-1110 UDC fills the Control FIFO with the command from the Host and the
CPU reads the command from the Control FIFO once it has arrived. The SA-1110 UDC will do a
partial decode of the command to determine if the CPU is going to be filling the Control FIFO with
data to send to the Host. If so, the direction is turned around to accept data from the CPU and have
the SA-1110 UDC transmit the data. If the command is such that no data will be required from the
SA-1110 UDC, then turn-around will not take place.
The only time the CPU may write to the Endpoint 0 Control FIFO is when a valid command from
the Host has been received, and that command requires transmission of a response, e.g., a
GET_DESCRIPTOR command.