Filter
Top Products
70 SA-1110 Developer’s Manual
Clocks
baud rates, then the 3.6864 -Hz oscillator may be replaced with a 3.5795-MHz crystal to generate
frequencies as shown in Table 8-1.The second oscillator is connected to a 32.768-kHz crystal. The
output of this oscillator clocks the power management controller and the real-time clock (RTC).
See Appendix B, “3.6864–MHz Oscillator Specifications” and Appendix C, “32.768–KHz
Oscillator Specifications” for detailed specifications of the crystal oscillators.
8.2 Core Clock Configuration Register
The core clock frequency is configured by software through the core clock configuration field
(CCF[4:0]) in the power manager phase-locked loop (PLL) configuration register (PPCR). This
field should be programmed during the boot sequence for the desired full-speed operation.
nRESET clears the field by selecting the lowest frequency operation.
See Section 9.5, “Power Manager” on page 9-99 for the physical address used to access this
register.
Table 8-1 shows the core clock frequency as a function of the CCF setting.
The actual core clock (DCLK) can switch between being driven by the high speed core clock
(CCLK, set by CCF[4:0]) and the memory clock (MCLK), which runs at half the frequency of
CCLK. CCLK is used except when the SA-1110 is waiting for fills to complete after a cache miss.
At reset, clock switching is disabled and the DCLK is driven by MCLK. Clock switching can also
be disabled by writing to CP15 register 15 with OPC_2 = 2 and CRm = 2 (see Section 6.2.14).
Clock switching is enabled by writing to CP15 register 15 with OPC_2 = 2 and CRm = 1.
Disabling clock switching only disables switching for DCLK; it does not force the DCLK to
MCLK. However, DCLK can be forced to MCLK by forcing an instruction or data cache miss after
clock switching is disabled.
Table 8-1. Core Clock Configurations
CCF[4:0] Core Clock Frequency in MHz
3.6864-MHz Crystal Oscillator 3.5795-MHz Crystal Oscillator
00000 59.0 57.3
00001 73.7 71.6
00010 88.5 85.9
00011 103.2 100.2
00100 118.0 114.5
00101 132.7 128.9
00110 147.5 143.2
00111 162.2 157.5
01000 176.9 171.8
01001 191.7 186.1
01010 206.4 200.5
01011 221.2 214.8
01100– 11111 Not supported. —