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324 SA-1110 Developer’s Manual
Peripheral Control Module
11.10.13 HSSP Register Locations
Table 11-18 shows the registers associated with the HSSP block and the physical addresses used to
access them.
Table 11-17. UART Control, Data, and Status Register Locations
Address Name Description
0h 8003 0000 UTCR0 UART Control Register 0
0h 8003 0004 UTCR1 UART Control Register 1
0h 8003 0008 UTCR2 UART Control Register 2
0h 8003 000C UTCR3 UART Control Register 3
0h 8003 0010 UTCR4 UART Control Register 4
0h 8003 0014 UTDR UART Data Register
0h 8003 0018 — Reserved
0h 8003 001C UTSR0 UART Status Register 0
0h 8003 0020 UTSR1 UART Status Register 1
0h 8003 0024 –
0h 8003 005C
— Reserved
Table 11-18. HSSP Control, Data, and Status Register Locations
Address Name Description
0h 8004 0060 HSCR0 HSSP Control Register 0
0h 8004 0064 HSCR1 HSSP Control Register 1
0h 8004 0068 — Reserved
0h 8004 006C HSDR HSSP Data Register
0h 8004 0070 — Reserved
0h 8004 0074 HSSR0 HSSP Status Register 0
0h 8004 0078 HSSR1 HSSP Status Register 1
0h 8004 007C - 0h 8004 FFFF — Reserved
Note: HSCR2 resides within the same address space as the PPC.
0h 9006 0028 HSCR2 HSSP Control Register 2