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274 SA-1110 Developer’s Manual
Peripheral Control Module
5. This indicates that a new OUT packet is in the EP0 Buffer identifying a SETUP transaction. To
help track this, software uses its state machine, which is currently WAIT_FOR_SETUP.
6. Software reads into a local buffer an amount of data from the UDCD0 Data Register FIFO as
specified by UDCWC-WC bits. To read the data: a) read the UDCWC-WC bits, b) read
UDCCD0, c) re-read the UDCWC-WC bits, and d) keep reading UDCCD0 followed by the
UDCWC-WC bits until the UDCWC-WC bits decrement.
7. After parsing the data, software recognizes this is a Control Read command, at which point
software starts loading the UDCD0 Data Register FIFO with the first packet of data and sets
the internal state machine to EP0_DATA_STAGE_XMIT.
8. Software then clears the UDCCS0-OPR bit by writing a 1 to the UDCCS0-SO bit and sets the
UDCCS0-IPR bit, telling the SA-1110 UDC to transmit the data on the next IN. (The SA-1110
UDC should have been NAKing all requests on this EP until the UDCCS0-IPR bit was set.)
An Open Host Controller Interface (OHCI) system will be sending repeated requests.
9. After the bit is set, the UDCCS0 should be 0000 0010b.
10. Return from interrupt.
11. The Host then issues an IN packet, which the SA-1110 UDC will send back to the Host. After
the Host ACKs the SA-1110 UDC, the SA-1110 UDC will clear the UDDCS0-IPR bit and
generate an interrupt.
12. Upon entering the ISR, software will examine its internal state machine and see that it is in the
state DATA_STAGE_XMIT and needs to transmit more data. The software loads the next 8
bytes of data into the UDCD0 Data Register, sets the UDCCS0-IPR bit, and returns from
interrupt. The internal state machine is left alone.
13. After the bit is set, the UDCCS0 should be 0000 0010b.
14. Return from interrupt.
15. Go back to step 11 until all of the data is transmitted or the last packet is a short packet.
16. Sometime during this sequence, instead of the Host sending an IN packet to get more data, the
Host sends a premature OUT STATUS stage telling the device it wants no more data.
17. This will cause an interrupt.
18. When this happens, the UDCCS0-OPR and UDCCS0-SE bits - 0010 0001b get set indicating a
premature STATUS occurred.
19. In the ISR, the software will see that its machine state is DATA_STAGE_XMIT. It must
interpret this as a premature STATUS stage. The software should then clear the UDCCS0-SE
bit by writing a 1 to the UDCCS0-SSE bit, and clear the UDCCS0-OPR bit and sets the
UDCCS0-DE bit by simultaneous writing to the UDCCS0-SO and UDCCS0-DE bits. The
UDCCS0 should be 0001 0000b.
Note: There is a possibility of an interrupt occurring while processing the DATA_STAGE_XMIT state
thereby setting the OPR/SE bits while software tries to write data to the FIFO and set the IPR bit. A
timeout should be incorporated in performing these steps, and the OPR bit should be checked and
acted upon before returning from the EP0 ISR.
20. Software changes its internal state to WAIT_FOR_SETUP. The software will clean up any
local data buffers.