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SA-1110 Developer’s Manual 293
Peripheral Control Module
Each bit in UDCSR is controlled by a mask bit in UDCCR. These mask bits, when set, will prevent
corresponding status bits (interrupt requests) in UDCSR from being set. If the mask bit in UDCCR
for a corresponding status bit in UDCSR is cleared and a corresponding interruptible condition
occurs, the corresponding status bit in UDCSR will be set. To clear status bits in UDCSR, the CPU
must write ones to the corresponding status bits. The SA-1110 UDC’s logically ORed interrupt
request will be active as long as the value of UDCSR is non-zero.
Note: Due to the internal synchronization required by the SA-1110 UDC configuration registers, it is
possible for the CPU to write to the SA-1110 UDC registers and FIFOs too fast. So, a single write
to the SA-1110 UDC must be completed before another write may take place. To ensure that a
single write is completed, it is necessary to observe the effect of the write before another write may
take place. This can be accomplished by writing to a SA-1110 UDC register and then reading back
the same register two times. The second read-back should produce correct data.
11.8.13.1 Endpoint 0 Interrupt Request (EIR)
The EIR bit is cleared to 0 by the CPU writing a 1 to it. The EIR bit gets automatically set to 1 if
the EIM bit in UDCCR is cleared to 0, and if either of the following conditions occur in UDCCS0:
• the OPR bit is set to 1
• the IPR bit is cleared to 0
• the DE bit is cleared to 0
• the SE bit is set to 1
0h 8000 0030 UDCSR Read/Write (Clear)
7 6 5 4 3 2 1 0
Reserved RSTIR RESIR SUSIR TIR RIR
EIR
Reset
0 0 0 0 0 0 0 0
Bits Name Description
0EIR
Endpoint 0 interrupt request (read/write clear).
1 – Endpoint 0 needs service.
1RIR
Receive interrupt request (read/write clear).
1 – Receive Endpoint (1) needs service.
2TIR
Transmit interrupt request (read/write clear).
1 – Transmit Endpoint (2) needs service.
3SUSIR
Suspend interrupt request (read/write clear). SUSIR is cleared by writing a 1 to it.
1 – SA-1110 UDC received suspend signalling from the Host.
4RESIR
Resume interrupt request (read/write clear).
1 – SA-1110 UDC received resume signalling from the Host.
5RSTIR
Reset interrupt request (read/write clear).
1 – SA-1110 UDC was reset by the Host.
7..6 —
Reserved.
Always reads zero.