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26 SA-1110 Developer’s Manual
Introduction
1.4 ARM Architecture
The SA-1110 implements the ARM* V4 architecture as defined in the ARM Architecture
Reference, 28-July-1995, with the following options:
1.4.1 26-Bit Mode
The SA-1110 supports 26-bit mode but all exceptions are initiated in 32-bit mode. The P and D bits
do not affect the operation of SA-1110; they are always read as ones and writes to them are
ignored.
1.4.2 Coprocessors
The SA-1110 supports MCR and MRC access to coprocessor number 15. These instructions are
used to access the memory-management, configuration, and cache control registers. In addition,
coprocessor 15 provides control for read buffer fills and flushes, and hardware breakpoints. All
other coprocessor instructions cause an undefined instruction exception. No support for external
coprocessors is provided.
1.4.3 Memory Management
Memory management exceptions preserve the base address registers so that no code is required to
restore state. Separate translation lookaside buffers (TLBs) are implemented for the instruction and
data streams. Each TLB has 32 entries that can each map a segment, a large page, or a small page.
The TLB replacement algorithm is round robin. The data TLBs support both the flush-all and
flush-single-entry operations, while the instruction TLBs support only the flush-all operation.
1.4.4 Instruction Cache
The SA-1110 has a 16 Kbyte instruction cache (Icache) with 32-byte blocks and 32-way
associativity. The cache supports the flush-all function. Replacement is round robin within a set.
The Icache can be enabled while memory management is disabled. When memory management is
disabled, all memory is considered cacheable by the Icache.
1.4.5 Data Cache
The SA-1110 has an 8 Kbyte data cache (Dcache) with 32-byte blocks and 32-way associativity.
The cache supports the flush-all, flush-entry, and copyback-entry functions. The copyback-all
function is not supported in hardware. This function can be provided by software. The cache is read
allocate with round-robin replacement.
The Dcache has been augmented with a 16-entry, two-way set associative minicache that allocates
when the MMU b and c bits are 0 and 1, respectively. This cache is accessed in parallel with the
main Dcache. Unlike the main data cache, the minicache implements a least-recently-used (LRU)
replacement algorithm. This cache is useful for applications that access large data structures and
would normally thrash the main Dcache. Instead, these data structures can be mapped so that they
allocate into the minicache and only replace data from the same structure.