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276 SA-1110 Developer’s Manual
Peripheral Control Module
Case 4: EP0 Control Write with a Premature Status Stage
1. At the beginning of the program, software initializes the internal state machine to
WAIT_FOR_SETUP.
2. Host sends a SETUP command.
3. SA-1110 UDC generates an EP0 Interrupt.
4. The software then determines the UDCCS0-OPR bit is set - 0000 0001b.
5. This indicates that a new OUT packet is in the EP0 Buffer identifying a SETUP transaction. To
help track this, software uses its state machine, which is currently WAIT_FOR_SETUP.
6. Software reads into a local buffer an amount of data from the UDCD0 Data Register FIFO as
specified by UDCWC-WC bits. To read the data: a) read the UDCWC-WC bits, b) read
UDCCD0, c) re-read the UDCWC-WC bits, and d) keep reading UDCCD0 followed by the
UDCWC-WC bits until the UDCWC-WC bits decrement.
7. When parsing the data in the buffer, software may see this is a Control Write command e.g. Set
Descriptor and sets the internal state machine to DATA_STAGE_RCV. The software clears the
UDCCS0-OPR bit by writing a 1 to the UDCCS0-SO bit, the UDCCS0 register should now be
0000 0000b.
8. Also, to allow a premature status stage, software must load a zero length packet into the
transmit FIFO by setting the IPR bit.
9. Return from interrupt.
10. The Host then issues an OUT packet, and the SA-1110 UDC issues an EP0 interrupt.
11. Upon entering the ISR, software sees the UDCCS0-OPR bit set - 0000 0001b, software will
have to examine its internal state machine and see that it is in the state DATA_STAGE_RCV
and needs to receive more data.
12. Software reads the amount of data from the UDCD0 data register determined by the
UDCWC-WC bits into a write command buffer and clears the UDDCCS0-OPR bit, the
UDCCS0 register should now be 0000 0000b.
13. Return from interrupt.
14. Go back to step 10 until all of the data is received.
15. Sometime during this sequence, instead of the Host sending an OUT packet to send more data,
the Host sends a premature IN STATUS stage telling the device it wants to send no more data.
16. Since we had loaded a zero length packet in step 8, the IN will result in the SA-1110 UDC
sending a zero length data packet back to the Host.
17. This will cause an interrupt.
18. When this happens, the UDCCS0-OPR and UDCCS0-SE bits - 0010 0001b get set indicating a
premature STATUS occurred.
19. In the ISR, the software will see that its machine state is DATA_STAGE_RCV. It must
interpret this as a premature STATUS stage. The software should then clear the UDCCS0-OPR
and the UDCCS0-SE bits by writing a 1 to the UDCCS0-SO and UDCCS0-SSE bits, and
change its internal state to WAIT_FOR_SETUP. The software will clean up any local buffer
pointers.