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40 SA-1110 Developer’s Manual
ARM Implementation Options
Interrupt disable flags are set where required to prevent otherwise unmanageable nestings of
exceptions. In the case of a reentrant interrupt handler, R14 and the SPSR should be saved onto a
stack in main memory before reenabling the interrupt; when transferring the SPSR register to and
from a stack, it is important to transfer the whole 32-bit value, and not just the flag or control fields.
When multiple exceptions arise simultaneously, a fixed priority determines the order in which they
are handled. The priorities are listed later in this chapter. Most exceptions are fully defined in the
ARM Architectural Reference. The following sections specify the exceptions where the SA-1110
implementation differs from the ARM Architectural Reference.
SA-1110 initiates all exceptions in 32-bit mode. When an exception occurs while running in 26-bit
mode, the SA-1110 saves only the PC in R14 and the CPSR in the SPSR of the exception mode.
The 32-bit handler must merge the condition codes, the interrupt enables, and the mode from the
SPSR into R14 if a handler is to run in 26-bit mode.
3.2.1 Power-Up Reset
When the nRESET signal is low, SA-1110 stops executing instructions, asserts the nRESET_OUT
pin, and then performs idle cycles on the bus.
When nRESET is high again, SA-1110 does the following:
1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into
them. The values of the saved PC and CPSR are not defined.
2. Forces M 4:0 =10011 (32-bit supervisor mode) and sets the I and F bits in the CPSR.
3. Forces the PC to fetch the next instruction from address 0x0000 0000.
4. Based on the state of the ROM_SEL pin, fetches this first instruction from either 16-bit
(ROM_SEL low) or 32-bit (ROM_SEL high) space. The SA-1110 memory controller
assembles the data into words in the case of a 16-bit wide ROM.
At the end of the reset sequence, the MMU, Icache, Dcache, and write buffer are disabled.
Alignment faults are also disabled, and little-endian mode is enabled. During power-up, nRESET
must be negated no earlier than 150 milliseconds after VDD and VDDx are stable to allow the
internal 3.686-MHz oscillator to stabilize. After the negation of nRESET, the PLL begins its
internally timed locking sequence. Note that the assertion of nRESET is destructive because the
state of the real-time clock and the contents of DRAM are lost.
The SA-1110 has three types of reset. See Section 16.2, “Reset” on page 16-414 in the
Boundary-Scan Test Interface for details.
3.2.2 ROM Size Select
The ROM width may be selected using the ROM_SEL pin. This pin is sampled during the assertion
of nRESET. The value is stored in the memory controller for use during ROM accesses. If this
signal is high during RESET, then the ROM is selected to be 32 bits wide. If it is low during
RESET, then the ROM width is 16 bits. There is no provision for 8-bit ROMs in the SA-1110.