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246 SA-1110 Developer’s Manual
Peripheral Control Module
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11.7.9 DMA Channel 1 Current Address Register
DMA channel 1 current address register (DCAR1) is a 32-bit read-only register that is used by
DMA channel 1 to keep track of the address of the DMA transfer currently in progress or the
address of the next DMA transfer. Any time the LCD is first enabled
(LEN= 0 → 1) or the value in
the current address pointer register equals the calculated end address value, the contents of the base
address pointer register is transferred to the current address pointer. This register can be read to
determine the approximate line that the LCD controller is currently processing and driving out to
the display. It is also useful to read this register just before writing the DMA’s base address pointer
to ensure that the end of frame is not about to occur, which means that the base address pointer is
about to be transferred to the current address pointer. Note that DCAR1 is a read-only register that
is not reset and is not initialized until the LCD is first enabled, causing the contents of the base
address register to be transferred to it; question marks indicate that the values are unknown at reset.
0h B010 0010
DBAR1: DMA Channel 1 Base
Address Register
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA Channel 1 Base Address Pointer
Reset
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Bits Name Description
31..0 DBAR1
DMA channel 1 base address pointer.
Used to specify the base physical address of the frame buffer within off-chip memory. Value
in DBAR1 is transferred to current address pointer register 1 when LCD is first enabled
(LEN= 0 → 1) and when the current address pointer value equals the end-of-frame buffer.
DBAR1 should be written only when the LCD is disabled or immediately after an interrupt is
generated by the setting of the base address update (BAU) status bit. The base address
must be on a quadword boundary; the user must always write bits 0 through 3 to zero.