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SA-1110 Developer’s Manual 337
Peripheral Control Module
11.11.7.4 Receiver Begin of Break Status (RBB) (read/write, nonmaskable
interrupt)
The receiver begin of break status bit (RBB) is set when the receive logic detects a null character
(contains all zeros, including the parity bit), followed by a framing error, which indicates the start
bit is zero. In other words, a begin of break is detected when the receive line is held low for one
frame duration (whatever size the frame is programmed to). When RBB is set, an interrupt is
signalled, a single null frame is placed in the receive FIFO, the framing error bit is set, and all
subsequent null frames with framing errors are ignored (not placed within the FIFO). After RBB is
cleared by the user, it cannot be set again until the receiver end of break status (REB) bit is set. This
interlock is used to prevent added null characters from entering the receive FIFO, and also allows
the user to clear the RBB bit (clearing the interrupt) and wait for the receiver end of break interrupt
(described in the next section). This interlock is cleared when REB is set, when RXE is cleared, or
when the SA-1110 is reset.
11.11.7.5 Receiver End of Break Status (REB) (read/write, nonmaskable
interrupt)
The receiver end of break status bit (REB) is set when the receive pin transitions high (rising edge)
and the RBB interlock is currently set (described in the preceding section). In other words, an end
of break is detected after a begin of break is detected and the receive line transitions from low to
high (indicating a new frame is about to occur or the receiver is entering the idle state). When REB
is set, an interrupt is signalled, and the RBB interlock is cleared, allowing any future data frame to
be stored to the receive FIFO. After the bit is cleared, it cannot be set again until the receiver begin
of break status (RBB) bit is once again set.
11.11.7.6 Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt)
The error in FIFO flag (EIF) is a read-only bit that is set when any error bits (8 through 10) are set
within the bottom four entries of the receive FIFO and is cleared when no error bits are set within
the bottom four entries of the FIFO. When EIF is set, an interrupt is signalled and DMA requests to
empty the receive FIFO are disabled until EIF is cleared. To discover the source of the errors, the
user should check the state of the FRE, PRE, and ROR bits in UTSR1, then read the corresponding
value from UTDR. This procedure should be repeated until EIF is cleared because errors that are
present within any of the four lowest entries in the receive FIFO will set EIF. Once all error tags are
cleared from the bottom half of the receive FIFO, EIF is automatically cleared, which in turn,
clears the interrupt and reenables the receive FIFO DMA request.