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SA-1110 Developer’s Manual 65
Memory Management Unit (MMU) 7
This chapter describes the memory management functions.
7.1 Overview
The Intel
®
StrongARM
*
SA-1110 Microprocessor (SA-1110) implements the standard ARM
*
memory-management functions using two 32-entry fully associative translation buffers (TBs). One
is used for instruction accesses and the other for data accesses. On a TB miss, the translation table
hardware is invoked to retrieve the translation and access permission information. Once retrieved,
if the entry maps to a valid page or section, then the information is placed into the TB. The
replacement algorithm in the TB is round robin. For an invalid page or section, an abort is
generated and the entry is not placed in the TB.
7.1.1 MMU Registers
See Section 6.2, “Coprocessor 15 Definition” on page 6-56 foradescriptionoftheMemory
Management Unit (MMU) coprocessor 15 registers supported by the SA-1110.
7.2 MMU Faults and CPU Aborts
The MMU generates four faults:
• Alignment fault
• Translation fault
• Domain fault
• Permission fault
Alignment faults are generated by word loads or stores with the low-order two address bits
nonzero, and by load or store half words when the low-order address bit is a one. Translation faults
are generated by access to pages marked invalid by the memory-management page tables. Domain
faults and permission faults are generated by accesses to memory that are protected by the current
mode, domain, and page protection. See the ARM Architecture Reference for more information. In
addition, an external abort may be raised on external data accesses.
7.3 Data Aborts
The SA-1110 takes a data abort exception due to: MMU-generated exceptions, accessing reserved
memory space.