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134 SA-1110 Developer’s Manual
Memory and PC-Card Control Module
20 E1PIN
SDRAM clock enable pin 1 (SDCKE 1) level control/status.
Control/status bit for the SDCKE 1 pin and it is automatically cleared upon entering sleep
mode or upon hardware or sleep reset.
E1PIN can be cleared by program to cause a power-down command (if K1RUN=1 and/or
K2RUN=1, and SLFRSH=0). However, this capability should be used with extreme caution
because the resulting state prohibits automatic transitions for mode register set, read,
write, and refresh commands. E1PIN can be set by program to cause a power-down-exit
command (if K1RUN=1 and/or K2RUN=1, and SLFRSH=0). See Section 10.5.5.
Setting E1PIN is a part of the hardware or sleep reset procedure for SDRAM. See
Section 10.2.1.
21 K1RUN
SDRAM clock pin 1 (SDCLK 1) run control/status.
Control/status bit for operation (run or not) of SDCLK 1 and it is automatically cleared upon
entering sleep mode and upon hardware or sleep reset.
K1RUN also can be cleared by program. However, this capability should be used with
extreme caution because the resulting state prohibits automatic transitions for any
commands. See Section 10.5.5.
Setting K1RUN and/or K2RUN is a part of the hardware and sleep reset procedure for
SDRAM. See Section 10.2.1.
22 K1DB2
SDRAM clock pin 1 (SDCLK 1) divide by 2 control/status.
Control/status bit for clock divisor of SDCLK 1. When set, SDCLK 1 runs at one-half the
memory clock frequency. When clear, SDCLK 1 runs at the memory clock frequency This
bit is automatically set upon hardware or sleep reset.
24..23 — Reserved.
25 K2RUN
SDRAM clock pin 2 (SDCLK 2) run control/status.
Control/status bit for operation (run or not) of SDCLK 2 and it is automatically cleared upon
entering sleep mode and upon hardware or sleep reset.
K2RUN also can be cleared by program. However, this capability should be used with
extreme caution because the resulting state prohibits automatic transitions for any
commands. See Section 10.5.5.
Setting K1RUN and/or K2RUN is a part of the hardware and sleep reset procedure for
SDRAM. See Section 10.2.1.
26 K2DB2
SDRAM clock pin 2 (SDCLK 2) divide by 2 control/status.
Control/status bit for clock divisor of SDCLK 2. When set, SDCLK 2 runs at one-half the
memory clock frequency. When clear, SDCLK 2 runs at the memory clock frequency. This
bit is automatically set upon hardware or sleep reset.
27 — Reserved.
28 EAPD
SDRAM/SMROM clock enable pin (SDCKE [1:0]) auto-power-down enable.
If EAPD=1, each of the clock enable pins (SDCKE 0 for SMROM and SDCKE 1 for
SDRAM) will automatically deassert whenever none of the corresponding banks is being
accessed. EAPD and KAPD must be written to the same value. See Figure 10-5 and
Figure 10-17. Auto-power-down must not be enabled until all other SDRAM/SMROM
hardware or sleep reset procedures have been completed. See Section 10.2.1.
0h A000 001C MDREFR Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLFRSH
Reserved
KAPD
EAPD
Reserved
K2DB2
K2RUN
Reserved
Reserved
K1DB2
K1RUN
E1PIN
Reserved
K0DB2
K0RUN
E0PIN
DRI11
DRI10
DRI9
DRI8
DRI7
DRI6
DRI5
DRI4
DRI3
DRI2
DRI1
DRI0
TRASR3
TRASR2
TRASR1
TRASR0
Reset 1 ? 0 0 ? 1 0 ? ? 1 0 0 ? 1 * * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
* Upon hardware or sleep reset, K0RUN and E0PIN are set to the value of the SMROM_EN pin.
(Sheet 3 of 4)
Bits Name Description