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SA-1110 Developer’s Manual 117
System Control Module
9.6.2 Reset Controller Register Locations
Table 9-5 shows the registers associated with the reset controller and the physical addresses used to
access them.
2WDR
Watchdog reset.
0 – Watchdog reset has not occurred since the last time the CPU cleared this bit.
1 – Watchdog reset has occurred since the last time the CPU cleared this bit.
3SMR
Sleep mode reset.
0 – Sleep mode reset has not occurred since the last time the CPU cleared this bit.
1 – Sleep mode reset has occurred since the last time the CPU cleared this bit.
31..4 — Reserved
0h 9003 0004 RCSR Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SMR
WDR
SWR
HWR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits Name Description
Table 9-5. Reset Controller Register Locations
Address Name Description
0h 9003 0000 RSRR Reset controller software reset register
0h 9003 0004 RCSR Reset controller status register