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SA-1110 Developer’s Manual 83
System Control Module
9.2 Interrupt Controller
The SA-1110 interrupt controller provides masking capability for all interrupt sources and
combines them into their final state, either an FIQ or IRQ processor interrupt. The interrupt
hierarchy of the SA-1110 is a two-level structure.
The first level of the structure, represented by the interrupt controller IRQ pending register (ICIP)
and the interrupt controller FIQ pending register (ICFP) contain the all-enabled and unmasked
interrupt sources. The interrupt controller pending register (ICPR) shows both IRQ and FIQ
pending interrupts. Interrupts are enabled at their source and unmasked in the interrupt controller
mask register (ICMR). The ICIP contains the interrupts that are programmed to generate an IRQ
interrupt. The ICFP contains all valid interrupts that are programmed to generate an FIQ interrupt.
This routing is programmed via the interrupt controller level register (ICLR).
The second level of the interrupt structure is represented by registers contained in the source device
(the device generating the first-level interrupt bit). Second-level interrupt status gives additional
information about the interrupt and is used inside the interrupt service routine. In general, multiple
second-level interrupts are OR’ed to produce a first- level interrupt bit. The enabling of interrupts
is performed inside the source device.
In most cases, the root source of an interrupt can be determined through reading two register
locations: the ICIP or ICFP (depending on which interrupt handler the software is in) to determine
the interrupting device, followed by the status register within that device to find the exact function
needing service. When the SA-1110 is in idle mode (see the Section 9.5, “Power Manager” on
page 9-99), any enabled interrupt causes it to resume operation. The interrupt mask is ignored
during idle mode if the DIM bit in the interrupt controller control register (ICCR) is set to zero (0).
Figure 9-2 shows a block diagram of the interrupt controller.
Figure 9-2. Interrupt Controller Block Diagram
Interrupt Controller
Mask Register (ICMR)
Interrupt Source
Bit
Interrupt Controller
FIQ
Interrupt
IRQ
Interrupt
to
Processor
to
Processor
Interrupt Controller
Pending Register (ICPR)
Interrupt Controller
FIQ Pending Register (ICFP)
Interrupt Controller
IRQ Pending Register (ICIP)
3131
All Other Qualified
Interrupt Bits
Level Register (ICLR)