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116 SA-1110 Developer’s Manual
System Control Module
The following table shows the RSRR.
9.6.1.2 Reset Controller Status Register (RCSR)
The reset controller reset status register (RCSR) is used by the CPU to determine the last cause or
causes of the reset. The SA-1110 has four sources of reset:
• Hardware reset
• Software reset
• Watchdog reset
• Sleep mode reset
Each RCSR status bit is set by a different source of reset, and can be cleared by writing a one back to that
bit. Note that the hardware reset state of software, watchdog, and sleep mode reset bits is zero. The table
below shows the status bits within RCSR. For reserved bits, writes are ignored and reads return zero.
0h 9003 0000 RSRR Write-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SWR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
0SWR
Software reset.
0 – Do not invoke a software reset of the chip.
1 – Invoke a software reset of the chip.
Note: This bit is self-resetting, and is automatically cleared several system clock cycles
after it has been set.
31..1 — Reserved
0h 9003 0004 RCSR Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SMR
WDR
SWR
HWR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits Name Description
0HWR
Hardware reset.
0 – Hardware reset has not occurred since the last time the CPU cleared this bit.
1 – Hardware reset has occurred since the last time the CPU cleared this bit.
1SWR
Software reset.
0 – Software reset has not occurred since the last time the CPU cleared this bit.
1 – Software reset has occurred since the last time the CPU cleared this bit.